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'Universal' Memory Aims To Replace Flash/DRAM

Posted by Soulskill on from the runs-on-vapor dept.

siliconbits writes "A single 'universal' memory technology that combines the speed of DRAM with the non-volatility and density of flash memory was recently invented at North Carolina State University, according to researchers. The new memory technology, which uses a double floating-gate field-effect-transistor, should enable computers to power down memories not currently being accessed, drastically cutting the energy consumed by computers of all types, from mobile and desktop computers to server farms and data centers, the researchers say."

26 of 125 comments (clear)

  1. 10 Years away by Anonymous Coward · · Score: 2, Insightful

    This technology always seems to be less than 10 years away.

    1. Re:10 Years away by gmuslera · · Score: 5, Interesting

      I hope that xkcd is wrong this time. Would be nice to have most new mobile devices with that in 2 years.

  2. But I like volatility! by melikamp · · Score: 4, Interesting

    Volatility is actually useful for certain security policies: like storing sensitive passwords in computer memory and working with temporarily decrypted files.

    1. Re:But I like volatility! by pushing-robot · · Score: 3, Informative

      The first floating-gate in the stack is leaky, thus requiring refreshing about as often as DRAM (16 milliseconds). But by increasing the voltage its data value can be transferred to the second floating-gate, which acts more like a traditional flash memory, offering long-term nonvolatile storage.

      --
      How can I believe you when you tell me what I don't want to hear?
    2. Re:But I like volatility! by Simon80 · · Score: 4, Interesting

      Volatile memory is already vulnerable to reboot attacks, because the data takes a long enough time to rot. Paradoxically, non-volatility could increase security in these cases by making it more obvious that it's not OK to leave sensitive info sitting around in memory.

    3. Re:But I like volatility! by mypalmike · · Score: 2

      Also, we lose the "just reboot it" fix for all the crappy software we write.

      --
      There are 0x40000000 types of people: those who understand 32-bit IEEE 754 floating point, and those who don't.
    4. Re:But I like volatility! by purpledinoz · · Score: 3, Interesting

      I read somewhere that if you cool DRAM, the data can stay intact for up to 10 minutes. That's plenty of time to remove the modules and extract the data from them. But if this is really a big concern, I wonder if it's practical to zero the memory after a PC is shutdown. Kind of a background routine. Or maybe even short all the lines to drain the stored charges.

    5. Re:But I like volatility! by squizzar · · Score: 2

      When your memory's nonvolatile
      Nothing is forgot, nothing is forgot, nothing is forgot

      If your bits try to get at you
      flip 'em with a not, flip 'em with a not, flip 'em with a not

      security isn't easy y'all,
      no it's fsckin not, no it's fscking not, no it's fscking not

      With a triple-des key in some volatile ram,
      encrypt all your memory and hide it from the man?

    6. Re:But I like volatility! by ultranova · · Score: 3, Funny

      But if this is really a big concern, I wonder if it's practical to zero the memory after a PC is shutdown. Kind of a background routine. Or maybe even short all the lines to drain the stored charges.

      Why would you sell computers with such features? Are your customers terrorists?

      --

      Forget magic. Any technology distinguishable from divine power is insufficiently advanced.

    7. Re:But I like volatility! by kasperd · · Score: 2

      I wonder if it's practical to zero the memory after a PC is shutdown. Kind of a background routine.

      If you want the hardware to be modified slightly to achieve it, then it should be completely practical. DRAM doesn't write individual cells at a time. It reads out entire lines of bits into SRAM modifies it there and writes it back. Moreover it even periodically sweeps over the lines just reading them out and writing them back to refresh them.

      I don't know how long time the sweep takes, but for wiping the memory you could speed it up. The control logic have a number of outgoing lines with a binary number indicating which line of cells to read or write. Each line has a decoding unit to know when its number is up. If you added a line to select all lines simultaneously and OR that line with the output of the existing decoding unit, it sounds feasible that the control logic could in fact write the contents of the SRAM to all lines in parallel.

      If this works you could wipe memory in less than a microsecond.

      --

      Do you care about the security of your wireless mouse?
    8. Re:But I like volatility! by kasperd · · Score: 2

      but rebooting would have to include zeroing all of the memory.

      Not necessary. The operating system already has to assume there could be random garbage in all the memory it didn't touch. The operating system has to zero the memory before handing it to applications. And that is the case even if it was zeroed on boot. It could be a long time since the system was booted, and the memory may have been used for something in the meantime. Some operating systems keep a cache of zeroed pages that can be handed to applications as needed, others do it on demand.

      --

      Do you care about the security of your wireless mouse?
  3. Early DRAM by DCFusor · · Score: 4, Interesting

    though it had a short refresh time spec, would actually hold nearly all the bits for up to a minute, and we made early "digital" cameras out of them, charging up all the bits and letting light discharge the lit up pixels quicker than the others. It was a bit of a bear to figure out the pixel layout -- it wasn't in order, but we did it and even got to two bits or so per pixel resolution by taking more than one shot after a charge, different exposure times. One wonders why someone doesn't just work along those lines. Seems to me for most uses simply increasing the refresh time interval would save tons of power, and also complexity. If you could get it to a couple of days, I'd think that would be fine for most all portable devices, and you'd just use cheap flash as the disk, like now. I am guessing you'd lose some density, as the older, less dense DRAMs had large cells that stored more charge per bit, and that new lower voltage semis are also leakier, but it might be worth looking into anyway. I recall one case where the company I worked for designed some very early disk cache controllers. Well, actually I did about 90% of that. We used DRAM, but simply arranged the code so the basic idling operation (for example, looking for io requests or sorting the cache lookup table) took care of refresh anyway, wasn't too hard at all to manage that, and of course a block read or write always did a full page refresh. Made the thing a little bit faster, as there was never a conflict between refresh and real use in the bargain. This would also be trivial an any current opsys to get done. Probably happens by accident except in real pathological cases.

    --
    Why guess when you can know? Measure!
    1. Re:Early DRAM by RotsiserMho · · Score: 2

      Unfortunately, my guess is simply increasing the refresh time is only going to solve one problem. I'm not an expert on DRAM or anything but it seems to behave like a capacitor. Longer refresh times require larger capacitance. Large capacitance doesn't necessarily mean more power, but I think it would take more voltage to change the state of a bit (you'd have to reverse a larger charge).

      Also, the biggest problem with DRAM these days is speed (reads/writes per second). The best way to increase speed (without also increasing voltage, and thus power) is to decrease capacitance since discharging a smaller charge is faster -- not to mention it would generate less heat, which leads to higher density and higher speeds, which is what the DRAM market is really after.

    2. Re:Early DRAM by sxeraverx · · Score: 4, Interesting

      You are correct. Currently, DRAM stores information as a N-channel MOSFET attached to a capacitor. This MOSFET is leaky. There's no getting around this leakage. This leakage acts to discharge the capacitor where the bit is stored.

      You can try to decrease this leakage in a number of ways. You can increase the threshold voltage of the gate, but that means you'd have to increase the voltage the DRAM operates at as well, or else you wouldn't be able to charge the capacitor. This means you'd increase the energy-per-operation of the DRAM cell, because you'd have to charge the capacitor up more. You'd burn up more power, because the leakage is proportional to the operating voltage, but the charging energy is proportional to the square of the voltage.

      Alternatively, you could increase the capacitance. But this means that the capacitor would take longer to charge, slowing down every operation. Also, doubling the capacitor size means doubling the energy it stores (and therefore burns with every operation). It also makes the DRAM cells bigger, meaning you can't fit as many on a silicon wafer.

      Neither of these is what you want to do. In fact, you want to do the opposite for traditional DRAMs. It's counterintuitive, but you get more density, more speed, and less power by increasing the refresh rate (or rather, increasing the refresh rate is a side-effect of all of those). Unfortunately, lithography limits and quantum mechanics mean we're having a hard time going any smaller.

      It's truly amazing what we can do. The oxide layer (essentially a layer of quartz glass between metal and silicon) on a MOS these days is 5 atoms thick. We're going to have to come up with something that relies on something other than the traditional semiconductor effects if we want to continue forward.

  4. Interesting by c0lo · · Score: 3, Interesting
    TFA

    "We believe our new memory device will enable power-proportional computing, by allowing memory to be turned off during periods of low use without affecting performance," said Franzon.

    Huh! A new chapter opens in the "program/OS optimization" - heap fragmentation will have an impact on the power your computer consumes, even when not swapping (assuming the high density and non-volatility will render HDD obsolete... a "no more swapping, everything is non-volatile-RAM, with constant addressing cost" becomes plausible).

    --
    Questions raise, answers kill. Raise questions to stay alive.
    1. Re:Interesting by VortexCortex · · Score: 2

      "no more swapping, everything is non-volatile-RAM, with constant addressing cost" becomes plausible

      Wouldn't Non-Volatile memory just be called memory esp. given that, by definition, memory recalls past events.

      This family of memory is not only plausible, it has existed before -- it is how the model of a "Turing Machine" operates. In fact, our first reel to reel magnetic memory systems had this "non-volatile memory" of which you speak due to the absence of large quantities of RAM (we had sequential access memory instead), programs were executed as read from tape, and variables were often interleaved with instruction codes because seek time was a huge performance issue.

      On another note: Perhaps the "no more swapping" model you speak of would draw less power if it used swapping to help cope with fragmentation? Or, perhaps each allocation unit (page), could be turned on or off individually.

  5. Oops, I knew I did something wrong... by Mr+Z · · Score: 3, Funny

    The memory breakthrough was working on had the speed of flash and the volatility of DRAM. It was pretty dense though...

    --
    Program Intellivision!
    1. Re:Oops, I knew I did something wrong... by jiteo · · Score: 2

      I forgot the memory breakthrough I was working on...

  6. Re:HP by afidel · · Score: 3, Informative

    Coming in 2013 according to this article from last year.

    --
    There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
  7. Cost/Byte? by artor3 · · Score: 3, Insightful

    Where does it get the power for the non-volatile write? It would have to have a battery or capacitor built in, in case of sudden loss of power. It would also need low voltage detection for the same reason. How does all of this end up affecting the cost and density? We already have non-volatile SRAM based on the same principles (warning: article sounds like it was lifted from a press release).

    The reason we use DRAM as computer memory is because it's really, really cheap. If nvDRAM ends up having a significantly highly cost per byte, I doubt it'll see much use. Especially when one considers the ever-falling price point for solid-state drives.

  8. say goodbye to volatility! or? by moxsam · · Score: 2

    So it's time to think about the next step: overwrite before freeing memory.

    I don't worry at all, it becomes a software problem, not a hardware problem. If only everyone overwrote unused memory...

  9. Finally! by Max+Littlemore · · Score: 4, Funny

    Whatever year it it comes to market, you can be sure of one thing....
    That will be the year of Multics on the desktop.

    --
    I don't therefore I'm not.
  10. meh... by White+Flame · · Score: 2

    I think memristors sound a lot more usable than this setup.

    Given the other thoughts about heap fragmentation and such things, I don't know if it's reasonable to expect fine-grained "flush to NV and stop refreshing" application, but rather as a system-sleep sort of mechanism. Of course, if memory allocators and GCs are written in knowledge of keeping LRU data clumped together, it might be reasonable. The comments say flushing is done on a "line by line" basis, which I don't personally know how big or small that gets.

    One wonders exactly how much juice it takes to flush to NV, vs the standard draw of the DRAM-style mode of operation.

  11. "Drastically reduce" the 1W by koinu · · Score: 2

    Maybe in mobile sector 1W per SDRAM module is interesting, but on desktop computers it isn't. They should reduce the energy to keep ATX boxes switched off(!) to 0W, as it was with AT, where a mechanical switch was used to cut the PC from power. It is simply inacceptable to consume energy (usually over 5W) when something is completely down (yeah I know, there is wake-on-LAN etc, but 99% of people don't use it). That's why I have a big fat red switch on my multi-outlet power strip.

    1. Re:"Drastically reduce" the 1W by DamonHD · · Score: 2

      My entire primary server uses less than 5W when operating except when absolutely flat-out when it eats a whole 7W, so I agree with you!

      http://www.theregister.co.uk/2010/11/11/diy_zero_energy_home_server/

      Rgds

      Damon

      --
      http://m.earth.org.uk/
  12. Re:But... by maxwell+demon · · Score: 2

    No. But it might store it.

    --
    The Tao of math: The numbers you can count are not the real numbers.