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Cheaper, More Powerful Alternative To FPGAs
holy_calamity writes "Technology Review takes a look at a competitor to FPGAs claimed to be significantly faster and cheaper. Startup Tabula recently picked up another $108m in funding and says their chips make it economic to ship products with reconfigurable hardware, enabling novel upgrade strategies that include hardware as well as software."
Erm, no. This is kind of the opposite of delay lines. It's more like a pipeline, where each segment of the pipe is actually the same piece of silicon real-estate.
Your data goes through the entire pipeline, getting munged just as a pipeline would at each step, and comes out just how you want it.
Problem is, with a pipeline I can have a different datum in each segment. With this, one datum has to go through all the steps before I can feed another datum into the pipeline.
The pipeline gives me an N:1 speedup due to, well, pipelining. This gives me a 1:N cost reduction vs. that pipeline, but at the cost of all that pipelined speedup.
Just take that 1.6 GHz and divide it by N and you get his data throughput rate vs. a pipelined processor with N stages and a 1.6 GHz clock.
And if the original design only had 1 stage, but it filled up N squares of silicon, and his chip only takes 1 square, now it takes N cycles just to do the work of that original design. Again, divide that 1.6 GHz by N and you get his effective data rate.
So it's cheaper to fabricate, about the same price to program, makes your boards a hair cheaper (smaller packaging we'd hope), but it makes your stuff run hyper-slow.
Cheap chips for cheap toys.
Next!
The real problem with FPGAs is the painfully byzantine tools you have to use to deal with them. The chips themselves are fine.
There is a lot of room for disruption in the programmable logic tools industry. If this company is smart, they will focus on workflow and toolchain innovations, rather than becoming too distracted by shiny silicon baubles. Shorten the edit-simulate-synthesize-test cycle and you will make a lot of people happy.
Then again, you should never argue with a man who buys his ink by the gallon, or his wafers by the acre.
Yup. Especially write-once FPGAs.
Sometimes making an FPGA is cheaper than building an equivalent board. You can get preprogrammed cells for entire microprocessors now. And lots of other library cells. Build an entire custom computer into a single package, if you want.
It's not dirt-cheap, but it's easy, and saves an assload on inventory.
See Fractal antenna no multiple antenna's needed. The receiver part is a different story.
No mention of how easy these things are to program. Timing constraints will be very tight, and what happens if clock skew carries signals across folds? Any success depends on how well the accompanying tools can implement the standard synthesis flow to support multiple levels.
No, you're not doing any funky RF on-chip, unless someone is making specialized FPGAs with the RF goodies baked-in.
FPGAs are wizard for dev cycles, though, if your changes are only in the logical realm. No need to turn new boards; just reprogram the FPGA and get on with your life.
This guy's real problem is it's going to be as little as 1/N as fast as the N times bigger circuit he's replacing.
All of our product have some sort of reprogrammable logic. PLD , GAL , EPLD, CPLD , FPGA, and some the designers should have been shot for making.
Without it we would not be able to design a product and get it to market with any hope of turning a profit. It keeps engineering costs low allows us to make changes for regulatory requirements and allows end users to load new firmware and fix problems in the field.
Some of our products are niche and low volume and some of our products are very high volume and we're growing.
I'd go on a Vegan diet but the delivery time from Vega is too long. --brownkitty
I've got kicked out of school with an EE degree, gone into software business (yeah, I know), and never looked back.
Do they ship products, other than dev kits, with FPGA?
All the time. They tend to be low volume items with high unit cost. Cisco has been a big consumer FPGAs forever. It's not even all that uncommon to find FPGA's in consumer electronics, though they tend to be very small parts used a glue logic.
For sure. Don't worry about getting the hardware working exactly right, we'll ship it now and release an upgrade later.
You can do that with FPGAs, just go through a defunctionalization step which spits out a FSM. See Bill Harrison's work at U. of Missouri.
Xilinx already supports this. You can load multiple different .bit files (fully compiled FPGA file format) into flash and then just reprogram the FPGA as needed on the fly. Also, FPGAs are great for general glue logic and massive individual IO connections. They allow you to have very low level control over signals that is just not the same in a microprocessor. They will definitely not replace a microprocessor for general program flow but they give you much tighter control over signals and signal timing. Have the FPGA do the low level things then punt it to the processor.
Although, it would be very nice to have an FPGA that ran faster than ~400-500Mhz. High performance FPGAs really require super wide buses and routing that is a nightmare. A chip running at 3x the speed would mean my buses could be 1/3 the width to handle the same bandwidth. You'd be surprised at the end of the day just what percent of your chip is dedicated to routing and buffering between clock domains when you deal with multiple 128-256+bit buses.
Many IO cards use FPGAs.
I have seen them in interferometer controllers, motor servo boards, fast multi-io cards, etc. Most of the stuff is low quantity, expensive stuff ($5000+ per item), so it seems like its easier to put in an FPGA than creating a new chip for a few 100/1000 copies...
HI O WISE PRINCE. WHT TOOK U SO DAM LONG?
If you're designing an ASIC, one traditional method is to do your design, flash it to FPGA, test it, debug, repeat, and when you're done, send it out to the fab to get it burned into ASIC. So yes, it's hardware upgrades through programmable circuitry, and you might be doing multiple upgrades per day.
If you're doing small production runs of chips, for instance for custom hardware, you may want something that's fast but you're not going to make 10,000 of them so you don't want to pay the price of burning ASICs. (ASIC prices have gotten a lot cheaper in the last decade, and production cycles have gotten faster, but it still takes time and money.) So don't - just do the chip in FPGA. And just like providing firmware in EPROM, the fact that the chip's reprogrammable doesn't mean you'll necessarily be doing that in the field.
These guys are basically doing a smaller cheaper FPGA design, as far as I can tell from the article and the comments. Those sound like good things.
Bill Stewart
New Fast-Compression-only CPR http://preview.tinyurl.com/dy575ks
Teig estimates that the footprint of a Tabula chip is less than a third of an equivalent FPGA, making it five times cheaper to make, while providing more than double the density of logic and roughly four times the performance.
That is 6X more impressive than any other use of factors in a sentence... ever.
I think the biggest flaw is that manufacturers don't necessarily want to update your existing device -- they want you to buy a new one. So whether the technology exists affordably really doesn't matter.
Oliver's law of assumed responsibility: If you're seen fixing it, you will be blamed for breaking it.
the guy behind Tabula is behind a number of "failwins" in the electronics industry - a fail in that the technology ended up being pointless and rejected by the market, but wins in that his companies were all bought out by suckers for quite a bit of $$$$
two examples:
- X initiative (use 45 degree routing on chips) - look at http://www.xinitiative.org now - 100% dead. look at it, and all the wonderful claims he (and his sucker followers) made in archive.org.
- Simplex solutions - built a large number of poor quality EDA tools (poor because they never got adopted and so never got the real bugs worked out and features required for real work) but looked very shiny, so were sold to cadence for a fairly large sum of money (relative to the low dev. cost). All but one of the simplex tools (now called cadence QRC) has been EOLd by cadence, and QRC will be thrown out just as soon as anyone cares enough to replace it with something better.
You can bet Tabula, if it succeeds at all, will be another failwin. It will be bought by one of Xilinx or Altera (the current FPGA duopoly), a couple of minor good ideas will be incorporated into future products and the overwhelming majority of the Tabula technology will be promptly forgotten. ...why? I hear you ask?
The reason is simple: Steve Teig has realized that "spamming" technology really does work (for him) - he has figured out that he can leave it up to much larger corporations to figure out, in their own sweet time, why 99% of his ideas sound great but are actually pointless, in the months and years after they are fooled into acquiring his techno-spam through an acquisition.
From one of his many online bios:
He holds over 220 patents. In 2002, he broke Thomas Edison’s record for the number of patents filed by an individual in a single year.
Enough said.
Link to a better writeup, one that doesn't attempt strained architectural analogies (ignore the first paragraph or three, but do look at the comments).
Here's the thing people don't seem to realize: FPGAs *are* cheap.
Case in point: Xilinx XC3S50A. $5.75 at Avnet. Comes in a hobby-solderable VQFP and you can make it work on a 2-layer board. Add a SPI flash to boot from (or a nearby micro with ~50K of spare flash), an oscillator, and +3.3V/1.2V regulators for power and you're still under 10 bucks parts cost - in low quantity.
This chip is only bottom of the line, but it's full of awesome stuff - "DCM" clock multipliers that can let you run FPGA designs at 250+ MHz by multiplying up slow external clocks, three 18x18 multipliers that run at almost the same speed, three 2Kbyte SRAM blocks that you can use as instruction/data memory for processors (eg, a Picoblaze, which can run at 100+ MHz).
These are great little things to play with as a hobbyist. I've contemplated making an Arduino shield with a small, cheap FPGA for people to experiment with, but I never really could figure out any good way to get data and signals in and out of the chip in a way that shows off what FPGAs are really good at.
Because FPGAs are very expensive. The top end ones cost more than people want to spend on their entire desktop, just for that one chip. Custom logic will always be cheaper, because it only gives you what you need.
Also, your idea of shutting it down to save power doesn't really help. All chips go to sleep when not in use, there's nothing special about FPGAs in that respect.
Plenty of tools like oscilloscopes now use FPGA's. Low end FPGA's are a couple of dollars tops, which is cheaper then the purchase plus production costs for a bunch of discrete chips.
A lot of hobbyist producers make designs with those low end FPGA's because it can be cheaper to use one FPGA over a whole bunch of products rather then stocking equivalent discrete IC's (ie you can buy an FPGA in 1000 quantities and use it across 10 products).
Of course this new product is just a cheaper FPGA, and their marketing claims are bullshit. Consumer electronics producers do not want upgradeable or repairable electronics. They want to be in the "fashion" business like Apple and sell new "upgrades" every year.
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CINC, 4th Penguin Legion
The disruption you mention almost happened in the early 90's. NeoCAD produced a compete competing tool chain for Xilinx FPGAs, including the place and route, for the then state-of-the-art 4000 series. Their software was better than Xilinx's, including things like a graphical layout editor. Xilinx was having none of it and bought NeoCAD. Quite a few NeoCAD features made it into the Xilinx software, eventually. Soon after that Xlininx started publishing less information on their FPGA's interconnect networks, and there has never been another attempt at writing such software.
Personally, I think writing a clone of the Xilinx software, today, is the wrong thing to do. It would be less effort to design and manufacture an "open source" FPGA, and write the necessary software from scratch, than to reverse engineer Xilinx's place and route.
...but it has fast context switching built-in. And you can't control when the contexts switch, they always go in order (as they should, since they're all statically assigned, and are different parts of a single problem, rather than separate problems).
For those that don't know how FPGAs work, here's a basic crash course: they have lots of blocks, each one has a look-up table (say a 4-LUT; 4 inputs, 1 output). The LUT is basically a "read-only" RAM with 4 address bits (so 16 addressable locations), and one data bit. The RAM can be rewritten (this is what is done when they program an FPGA), but it's fairly slow. Tabula changes it up a bit so that each addressable location is 8 bits instead of 1 bit. Since transistors are basically free on an FPGA (they're wire-dominated), this doesn't cost much, and it means that they can time-share pieces of silicon for different purposes without the penalty of reprogramming the chip. Then, each cycle, it'll pick a different one of the 8 bits (though the address, or inputs to the 4-LUT, may be changing at the same time).
It's a fairly straightforward idea, though there's a fair amount of complexity added to the design tools.
However, it's not free. You now have lots of high-speed logic, which is probably using tons of power, and it's switching frequently, which is using tons more power, and even when it's not, it's probably fairly leaky, using even more power. Effectively, you have a 1.6 GHz chip, but to you it seems like it's only running at 200 MHz - but it can do ~8 times more processing per silicon area. You might also think of it as being similar to the Pentium 4 integer units; they ran at twice the clock speed of the rest of the chip, so it seemed like there were twice as many of them (so a single IU could do an add in the first half of a core clock cycle, and a subtract in the second, computing two instructions per cycle).
So this chip is basically trading latency for computing power. The more operations you need to do, the slower it will run, because it'll take more of their folds to implement your logic.
ASICs actually got more expensive. The individual ASIC is cheaper now, but the non recurring costs of making a ASIC went up a lot. Smaller process nodes need more masks and more complicated masks.
If your mask set is $2.000.000 and you are going to sell ASICs 10,000 made with it, even if the individual ASIC is free after paying for the masks, you are still at $200 per piece. The $100 FPGA is a better option then and at 10.000 pcs you are going to get a pretty large fpga for $100.
Jan
How about audio processing? Are they any good at that? Because anything really customizable seems to cost an arm and a leg when it comes to musical gear. You could write a plugin for Audacity that interacted with it, maybe letting guys like me offload some of the processing on effects?
If there is one place that F/OSS could really take some serious marketshare it would be musical creation. Most of us musicians have no problem with tinkering, and as long as we can do cool things with it we don't mind if we have to get a little fiddly, and finally Audacity is already F/OSS and frankly is pretty kick ass, so there is already great software to plug these things into. If these chips would work good for audio I could see F/OSS DIY home studios becoming hot with musicians, especially seeing as how crazy the prices for some of the proprietary stuff is.
ACs don't waste your time replying, your posts are never seen by me.
The FPGAs needed to replace even fairly lousy shipping discrete GPUs cost on the order of $10k each. To replace a decent middle-of-the-pack GPU with an FPGA, you'd need to spend on the order of $100k in chips just for one board. Never mind that the board would consume on the order of 1kW of power, and good luck if your board assembly house messes something up: you lose a house's worth of hardware. It'd probably cost a couple $k to get the board assembled!
A successful API design takes a mixture of software design and pedagogy.