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Inside NVIDIA's Massive Hardware Emulation Lab
MojoKid writes "NVIDIA recently decided to give the public a look at their massive investment in hardware emulation technologies. Hardware emulators are specialized systems that can be programmed to emulate any specific architecture. In NVIDIA's case, a standard x86 system is connected to a powerful hardware emulator that's been pre-programmed to emulate a GeForce GPU that's still under design. The testbed generates the code in question and sends it over to the emulator, which then executes and returns the output. The emulators are massive machines that can be connected together and scaled for capacity and performance. NVIDIA's Indus emulator can emulate up to two billion gates and in their entire facility, the company can emulate up to 4 billion total."
Why not link directly to the blog post instead of a rewording of it?
http://blogs.nvidia.com/2011/05/sneak-peak-inside-nvidia-emulation-lab/
Also, "gates" probably refers to Boolean logic gates.
I think the term "gates" is abused and misused here, and in other articles. Not everything that goes on chip is a "logic gate", not even "gate", and they ought to be simulated as well. Think about clock modulators, PLL's, DCMs, for example. Other more esoteric thing exists.
Doing a transistor-level simulation is also very expensive here. This is usually done on the low-level blocks only (and perhaps before going into silicon).
What you simulate most of the time is RTL - Register Transfer Level. This includes not only plain logic paths, but synchronous elements like memories, flip-flops, and others.
Being used to RTL simulation (I do a lot), those numbers are absolutely impressive. I often spend an hour simulating only a few microseconds. And the outputs of simulation are *huge* - imagine you have 1 million signals on the chip, and your freq. is 1MHz. This means you will retrieve 1 million * 1 million signal data for a one second simulation.
Álvaro