Slashdot Mirror
FPGA Bitstream Security Broken
NumberField writes "Researchers in Germany released a pair of papers documenting severe power analysis vulnerabilities in the bitstream encryption of multiple Xilinx FPGAs. The problem exposes products using FPGAs to cloning, hardware Trojan insertion, and reverse engineering. Unfortunately, there is no easy downloadable fix, as hardware changes are required. These papers are also a reminder that differential power analysis (DPA) remains a potent threat to unprotected hardware devices. On the FPGA front, only Actel seems to be tackling the DPA issue so far, although their FPGAs are much smaller than Xilinx's."
Is this the good kind of security breach, which enables end users to do new things with their FPGAs? Or the bad kind, that enables attackers to do malicious things with others FPGAs? Or both?
Give me Classic Slashdot or give me death!
As transistors switch they create little glitches in the power supply, or rather they consume a little more or less current than at the previous steady state (where steady state may be nanoseconds long). By correctly interpreting the changes in current consumption the encryption key can be read.
For the car analogy (this is slashdot after all) think of it as monitoring fuel flow to extrapolate acceleration, speed and distance.
An FPGA is sort of like a PROM except that instead of memory circuits you program logic circuits into it.
If this hack allows people to reverse-engineer the chip, they can basically dump its logic diagram, which means that they could copy it. As I understand it, it's normally pretty hard to reverse-engineer a microchip, so this is a pretty significant breakthrough.
An interesting blurb from the Actel linked page:
Many of the fundamental techniques used to defend against DPA and other side-channel attacks are patented by Cryptography Research, Inc. ... One of CRI's businesses today is licensing this portfolio of very fundamental patents. Nearly all the secure microcontrollers used in smart cards, set-top boxes, SIM cards for GSM phones and Trusted Platform Modules (TPM) for personal computers are built under license to CRI, amounting to about 4.5 billion chips per year in total.
Yet another critical set of concepts which should be obvious to anyone working in the field locked behind a paywall due to USPTO incompetence and/or malfeasance...
...to try to keep the power consumption constant, therefore not giving hints, if I understand correctly.
Uh, Linux geek since 1999.
I am referring to adding circuitry into the FPGA's themselves, so that the current consumption cannot be as easily used for side-channel attacks.
In a sense, think of adding additional NOT gates, within the FPGA itself, and their only purpose would be to always have the combination of an actual [data line + NOT] provide a sum of constant power consumption wherever the FPGA is doing anything that might leak side-channel info. None of the NOT gates would actually be part of processing actual data. At least, that is an idea of what kind of approaches they could try.
Uh, Linux geek since 1999.
Not everyone who complains on Slashdot is naive on patent realities, and the problem is real and ugly.
Aside from the legal fiction of the PHOSITA (Person Having Ordinary Skill In The Art), the intent of this clause by the framers was that it should not be possible for anyone to obtain a patent on something that would be obvious to someone working in the field.
In this specific case, once the feasibility of power vector side channel attacks was understood, any ideas that should have been obvious to someone having ordinary skill in the applicable fields (cryptanalysis of side channels, EE, FPGA layout internals) should not be patentable.
While credit must be given to researches who discovered these attack vectors, the fact remains that the patents they obtained are broad enough to intersect essentially every idea a PHOSITA would come up with. While it is possible to interpret claims narrowly through the context of the background and description, juries often (especially in East Texas) fail to narrow interpretations sufficiently, and just attempting just a narrow interpretation will still cost you $1-3M in legal fees.
If your job includes evaluation of risk of patent infringement (which mine does, for one of the worlds largest companies) then you would understand that the combination of lowering the bar on "obvious" and "prior art", along with the challenges that venue shopping presents, have created a situation where it has become nearly impossible to do anything interesting without infringing many patents that should NOT have been issued.
You miss the point - the researchers discovered an application of the laws of physics to cryptanalysis. Cool, interesting, but not inherently patentable. Then they patented every way to fix that problem, many of which would be obvious to someone skilled in the art.
If I discover that 1+2 = 3, I cannot patent that equation. If I discover an application of that equation to a physical problem, the intent of the framers in patent law was that only a non obvious application may be patented. The fact that they discovered the problem doesn't (at least by law) eliminate or nullify the PHOSITA requirement.
The researchers found a hard to find problem, then patented the obvious solutions to that problem.
This is one of the problem with patents in general - patents are being issued where the person "skilled in the art", i.e. someone who has the same degree of specialization, would have developed the same solution, and the USPTO no longer makes a reasonable effort to prevent that.
Note that most FPGAs (and all of Xilinx's) are SRAM based - the bitstream has to generally be loaded from an external memory IC at boot-time.
Not true, the Xilinx Spartan-3AN can store the bitstream in internal flash memory.
That is the only family with that feature though.