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Oracle's Sparc T5 Chip Evidently Pushed Back to 2013
Mark Hachman writes in Slash Datacenter that the Sparc T5 chip Oracle announced earlier this year apparently won't be ready until sometime in 2013. John Fowler, executive vice president, Systems, Oracle, presented at Oracle Open World a chart outlining highlights of Oracle's plans for the future.
"But Fowler also skipped over some bad news: an apparent delay for the Sparc T5. A year ago, Oracle’s Sun division announced the Sparc T4—and according to Fowler, Oracle chief Larry Ellison set a very high bar for the next iteration: double the performance while maintaining app compatibility on an annual basis. Apparently, that didn’t quite happen with the T5; Oracle had the opportunity to announce a T5-based server, and didn’t. That’s a bit of bad news for the Sun design team, which already had to watch Intel’s Xeon chief, Diane Bryant, give the preceding keynote. ... As detailed at this year’s Hot Chips conference, the T5 combines 16 CPU cores running at 3.6 GHz on a 28-nm manufacturing process. Continuing the trend of hardware acceleration of specific functions, Sun executives claimed the chip would lead in on-chip encryption acceleration, with support for asymmetric (public key) encryption, symmetric encryption, hashing up to SHA-512, plus a hardware random number generator."
Someone is still buying that shit?
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Companies continue to force non-free software onto unsuspecting victims too.
Actually the fine article is about hardware; processors to be specific.
If I was heavily invested in Solaris I would be interested in the Sparc T5. Here are some excerpts from this Register article:
The Sparc T5 chip is more than just a shrunken Sparc T4 processor, which Oracle revealed at last year's Hot Chips conference and then started shipping in systems as 2011 wound down. The Sparc T4s had eight of the new S3 generation of Sparc cores, and the 3GHz clock speed and tweaks to the instruction pipeline were designed to make it much better at single-threaded work than its Sparc T chip predecessors. The Sparc T4 is manufactured by Taiwan Semiconductor Manufacturing Corp using its 40 nanometer processes, and the sixteen-core Sparc T5 chip uses the popular 28 nanometer processes from TSMC that a number of processor and graphics card makers are employing in their latest devices.
Getting back to sixteen cores on the Sparc T5 die, each with eight threads for running heavily threaded work, is a good use of the process shrink. Oracle could have gone a simpler route and double-stuffed the sockets with slightly modified Sparc T4 designs, akin to what IBM is doing with its Power7+ processors in some server configurations, to get to that sixteen core level. But, for whatever reason, Oracle wants to have all of the cores on the same die and running on the same crossbar interconnect.
Before Fowler became an Oracle employee, he was in charge of the hardware division at Sun. And before that, he was in charage of x64 systems. I was working there at the time, and the word from on high was that putting the x64 guy in charge was a signal about our future direction.
Which of course, didn't happen. Sun's sales channels continued to view x64 systems as a way of migrating people to SPARC vis Solaris-on-x64. Which all our customers, who were already heavily invested in Windows and Linux, had no interest in. My big hope for the Oracle takeover was that Oracle's sales org (aside from being bigger than all of Sun) would be smarter than that and push x64 systems.
But Oracle has dratically reduced the models of x64 systems they sell. Officially, that's about a leaner product line and ending the special relationship with AMD. But I'm beginning to expect that the SPARC koolaid is as popular in Oracle as it was in Sun.
Glacial indeed, if they haven't already done it. Like the other 99% of the industry.
One has to be really dense not to see this trend. ALPHA is gone. MIPS is only used in embedded devices. Itanium and POWER are strictly legacy products. And yet people still believe that SPARC can survive in the server space.
I'd be sad too if I still worked at Sun. But not only does the failure of this product line no longer affect me, even abandoning SPARC completely would not save it. Computers are Dead.
Yeah, do not buy old Sun hardware thinking that you can get any useful support from third parties, or pick up a cheap support contract suitable for a sysadmin's home box or a dev workstation... or even download firmware for a device that is not covered by your current support contract. That sort of thing went away by or shortly after the time that Oracle bought Sun.
Oracle doesn't really care about ISV support for SPARC, and they probably like it if their big Oracle/SPARC sales included a hefty dose of high margin professional services to cover the customer's inexperience with the hardware platform, so why do they need ordinary people using SPARC anyway?
"You actually don't need to be open-minded about Oracle. You are wasting the openness of your mind..." - Bryan Cantrill, Fork Yeah!
-Snorbert, somewhere in the antipodes
Five years ago your comment would have made a lot of sense to me, but now you're talking about how everyone's gone X86 during the first massive movement away from X86 the industry's seen... smartphones and tablets are all computers that run on ARM processors, they're cleaning X86's clock in the only rapidly expanding market. And ARM's next core design is aimed at servers.
For the first time, Windows compatibility is mattering less and less as many users only use the web and web apps on their computers - opening the door to competing processors for the first time since the late 80's. At the same time, PC's continue to represent a smaller and smaller share of new CPU's, which are migrating to data centers, smartphones, and pads, which are even less dependent on X86 compatibility.
For the first time, the computational penalty of X86 instruction set translation for RISC cores may not outweigh the compatibility benefit for a significant portion of users. Increasingly, customers don't care about compatibility with existing X86 codebases. Like ARM, anyone with a new processor with compelling performance per watt might actually be able to sell the thing, without everyone assuming it's worthless if it won't run Windows.
Also, I wouldn't quite characterize POWER as a strictly legacy product, since IBM introduced the latest iteration, the power 7+, in August 2012, and is currently selling 15 different systems using Power7 processors. Not to mention the Xbox 360, Playstation 3, Wii, and not-even-out-yet Wii U that are all POWER based systems.
Can anyone tell me how to set my sig on Slashdot?
"If you were plowing a field, which would you rather use: Two strong oxen or 1024 chickens?" - Seymour Cray.
The devil is in the details. SPARC has lots of registers, very true. But it needs more user-accessible registers, because its address modes are simpler, and you need to do more address computations in registers. Register windows were like a fully associative cache for a few levels of your call stack... but then you have to save more stuff when you do a context switch, and I suspect they were part of why Sun was late to doing full out-of-order execution in their SPARC implementations.
I was a big fan of the early RISC chips, because that architectural style was bringing forth implementations which got much better bang per CPU transistor than other commercial chips at the time. That lead was eroded seriously by Intel with the Pentium Pro - certainly in terms of bang per buck - which was embarrassing for people who wanted to point out some inherent "elegance" or other timeless quality of RISC that was its great advantage. Whatever that counted for, Intel's designs and better process technology could more or less match with ugly old x86.
The time when you could play Top Trumps with computer architecture specs is really over. Decisions that were clear winners at a particular time, in terms of process technology, memory bandwidths, and compiler quality, can turn out not to be as optimal when the market, or what is cost-effective to produce, changes over time.
The T series SPARC chips came out of work done by Kunle Olukotun at Afara Websystems and then brought in-house by Sun. They represented a great point-in-time improvement for high parallelism, cache-unfriendly, integer server loads over what was under development inside Sun at the same time, especially when cost and power were taken into account. Some of those decisions in the T1 got revised for the T2 - one FPU for the whole chip turned into one FPU per core, for instance - but the per-die core count got halved for the T4, so again the Top Trumps viewpoint doesn't really illustrate whether one processor is better than another.
Bottom line is, does it run the stuff you want to run, for a good TCO?
-Snorbert, somewhere in the antipodes
For the first time, the computational penalty of X86 instruction set translation for RISC cores may not outweigh the compatibility benefit for a significant portion of users.
Yes and no.
Yes, in that it's always mattered. Intel can never be power competitive in the low end due to the expense of the x86 instruction decoder. Then again, neither can ARM which is why static 14/8 bitters like PIC dominate the truly low end. In the mid range ARM and others (but mostly ARM) will not be displaced by Intel for exactly that reason.
ARM dominate all the way to the beginning of the high end. However, once one hits the high end, and single thread performance goes up, again the decoder becomes a smaller and smaller fraction of the energy usage. The OoO unint and execution units dominate, as the OoO unit has to expend a lot of energy to keep the energy hungry execution units fed while they're ungated.
Users are now beginning to care about the high end on their phones, just about.
For fun, compare the FLPOS/Watt of an i7 Ivy Bridge to any other general purpose CPU. The Ivy Bridge one does surprisingly well, in fct I think it's pretty much a winner. Certianly compared to ARM. The reason is that as the performance goes up, the instruction decoder begines to pale in to insignificance.
It's the same old argument as always.
Intel will never hit the mid to low end, but the penalty almost disappears on the high end, and Intels better process and expertise in branch prediction dominates.
For now, phones are bumping into the bottom of the top end. In 5 to 10 years they will be firmly in it, and the landscape will be very different. In 10 to 15 years, cheaper smartphones (e.g. spiritual successors to something like the Galaxy Ace) will be comfortably inot the high end.
Arm will continue to dominate the upper low end to the top of the middle because of the decoder. But phones things will be moving well into the top end.
I'm defining low/middle/high by absoute performance and relative power tradeoffs between parts of CPUs.
SJW n. One who posts facts.