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AMD Licenses 64-bit Processor Design From ARM
angry tapir writes "AMD has announced it will sell ARM-based server processors in 2014, ending its exclusive commitment to the x86 architecture and adding a new dimension to its decades-old battle with Intel. AMD will license a 64-bit processor design from ARM and combine it with the Freedom Fabric interconnect technology it acquired when it bought SeaMicro earlier this year."
What's sad is how bad the former CEO fucked AMD by doing a total slash and burn on their engineering and R&D and pushing for cheaper automated layouts that simply don't cut it. The Athlon64 guys? GONE. The Cryix guys? GONE. they pretty much have their backs against the wall because the former CEO burned the fucking company to get a short term bounce, which I'm sure he cashed out on.
And anybody who thinks ARM will save them might be interested in some magic beans I have for sale, as ARM frankly doesn't scale very well and from the early looks ARM64 isn't gonna be really any better for power than the CULV Intel chips while having a HELL of a lot worse IPC. Frankly, and this is coming from someone who has been building AMD systems exclusively for awhile now and is still hanging onto AM3+ for all its worth, the only real selling point they had was "bang for the buck" but by burning R&D and killing Thuban the former CEO left them holding the bag without shit besides Bulldozer, which we all know blows too much power, is too damned hot, and frankly their octocores get stomped by Intel quads on IPC while using a third of the power.
I have to agree with the engineer in that link, they should have done the same thing Intel did with Core, go back to their earlier K8 designs and start from there just as Intel did with P3 mobile but now they just don't have the money or the time. I truly hope the Athlon64/Apple A6 chip designer they hired back can come up with a design to save the company because right now? Right now they really got nothing. Hell the former CEO even pulled the plug on Krishna, which would have been a sub 20w quad core bobcat, which is why all we're seeing now is minor speedbumps on a 3+ year old design. I swear they got fucked raw by bad management and I only hope they pull through. Maybe if they would have done this 4 years ago they could have the niche Nvidia now holds, but now? Its just not enough.
ACs don't waste your time replying, your posts are never seen by me.
It usually normally takes a day or so for replays to be posted but it should show up on the AMD Investor Relations Website (same site that hosted the live webcast).
ARM architectures are considered more energy-efficient for some workloads because they were originally designed for mobile phones and consume less power.
Fuck no. The ARM1 was released in 1987 as a coprocessor for Acorn's BBC Micro. They were designed for low power operation because the engineers were impressed with the 6502's efficiency. There weren't any significant mobile phone deployments until 18 years later in 2005.
I am trying to grasp, somewhat desperately, the events that must have taken place inside AMD headquarters when the CPU design team said they wanted to do hyper-threading. Having seen how badly Intel got knocked around when they did it, and the fact that for the price of duplicating a fair amount of the CPU, you are still only occasionally eking out a slight performance gain...and sometimes, a performance loss, their strategy doesn't make sense
Perhaps they looked at IBM or Sun's implementation of SMT instead. Adding a second context to the POWER series added about 10% to the die area and gave around a 50% speedup. If you have multithreaded workloads (especially on a server) then it can significantly improve throughput for two very simple reasons. The first is that when one context has a cache miss, the CPU doesn't sit idle, it can let the other core work. The second is that it makes branch misprediction penalties lower, because if you're issuing instructions alternately from two contexts you can get the instruction that the branch depends on a lot closer to the end of the pipeline than before you need to make the prediction. This also helps with various other hazards, so you don't need so much logic for out-of-order execution to get the same throughput.
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Also, there is nothing about ARM that inherently makes it more powersaving @ the same performance level than other RISC CPUs, be it SPARC, POWER, MIPS and so on.
I can think of several things. For Thumb-2, there is instruction density. MIPS16 does about as well as Thumb-1, but it is massive pain to work with. AArch64 doesn't (yet) have a Thumb-3 encoding, but one will almost certainly appear after ARM has done a lot of profiling of the kinds of instruction that CPUs like to generate. Even in ARM mode, the big win over the other RISC architectures is the it has fairly complex addressing modes, so you can do things like structure and array offset calculations in one instruction on ARM or 3-4 on MIPS. For AArch32, you also have predicated instructions. These make a big difference on a very low power chip, because you don't need to have any branches for small conditionals. For AArch64, most of these are gone, but there is still a predicated move, which is a very powerful version of a select instruction and lets you do mostly the same things. With AArch32 you have store and load multiple instructions, which basically let you do all of your register spills and reloads in a single instruction (the instruction takes a mask of the registers to save, the register to use as the base, and whether to post- or pre- increment or decrement it as two flags). With AArch64, they replaced this with a store-pair instruction, which can store two registers, and has the advantage of being simpler to implement (fixed number of cycles to execute).
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