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Everspin Launches Non-Volatile MRAM That's 500 Times Faster Than NAND
MrSeb writes "Alternative memory standards have been kicking around for decades as researchers have struggled to find the hypothetical holy grail — a non-volatile, low-latency, low-cost product that could scale from hard drives to conventional RAM. NAND flash has become the high-speed, non-volatile darling of the storage industry, but if you follow the evolution of the standard, you'll know that NAND is far from perfect. The total number of read/write cycles and data duration if the drive isn't kept powered are both significant problems as process shrinks continue scaling downward. Thus far, this holy grail remains elusive, but a practical MRAM (Magnetoresistive Random Access Memory) solution took a step towards fruition this week. Everspin has announced that it's shipping the first 64Mb ST-MRAM in a DDR3-compatible module. These modules transfer data at DDR3-1600 clock rates, but access latencies are much lower than flash RAM, promising an overall 500x performance increase over conventional NAND."
non-volatile, low-latency, low-cost
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Still completely impractical. It may improve with time, but I wouldn't hold my breath. They basically have to improve fast enough to catch up and then surpass Flash memory, which is difficult at best with the enormous lead Flash memory currently has.
I read the internet for the articles.
It uses a lot more power while you are using it. Because it runs 500x faster you have to use it for a lot less time though, and it doesn't need power to retain state.
It uses 5x more power for that 500x performance. Of course, people will think up new ways to use that kind of performance.
For those curious, it performs 500x faster than NAND, costs roughly 50x more than NAND, and uses 5x more power than NAND. All-in-all, not too bad, considering it's new technology and is actually shipping, but it definitely has limited applications at the moment. Assuming they can get the cost down a bit or come up with a few more ideas to reduce power consumption (it's actually worse in older MRAM), it could be something interesting in the near future. I'm guessing MRAM will be showing up more and more often in the next few years, since it seems like it's finally cracked the wall between "cool in the lab" and "semi-practical" after years of being stuck.
The whole point of MRAM is to avoid the limited duration of Flash type memories. Data is stored as a magnetic field. Flash stores data as an electric charge - but the method flash uses to put that charge the is destructive to the insulating layer that keeps it there.
It's actually very durable. "In contrast, MRAM requires only slightly more power to write than read, and no change in the voltage, eliminating the need for a charge pump. This leads to much faster operation, lower power consumption, and an indefinitely long "lifetime"." (https://en.wikipedia.org/wiki/Magnetoresistive_random-access_memory)
5x more power than NAND
This seems confusing to me, because arguably it's going to use significantly less power than NAND. If I have something to write and it takes NAND 10s at 10w to write it, that's 100J of energy. MRAM would take .02s at 50w, that's 1J of energy. Unless I'm missing something? Seems like they could have quoted that to be both more accurate and show their product in a better light.
They claim shipping, so... yeah, a product. However, not a retail product, from the sound of it. Nobody makes a populate-your-own SSD or such.
More importantly perhaps, MRAM supposedly doesn't suffer from the page problem that NAND requires. Individual bits are accessible for reading and writing conveniently, unlike NAND, which requires writing by page. In addition, MRAM is supposedly much more robust than NAND, surviving many more write cycles. It hasn't existed long enough to know this for sure, but in theory, these two advantages means an SSD controller for an MRAM SSD could be vastly simpler than the ones required for NAND. No need for wear-leveling or page rewrite logic. This should both reduce the expense of SSDs and increase their real world performance and reliability.
However, while the article summary blathers about "from hard drives to main memory", this is not a competitor to modern DDR SDRAM. Assuming the quoted 500X faster than NAND is accurate, MRAM latency should be on the order of 100 nanoseconds for a random read. (NAND read latency is on the order of 50 microseconds.) DDR SDRAM random read latency is on the order of 22 nanoseconds.
Having said that, it is comparable with SDRAM from a decade ago, which probably translates directly to modern mobile devices. Low power suspend mode using MRAM instead of SDRAM could conceivably lower mobile device power consumption and improve battery life. If manufacturers get really silly, in theory a mobile device could be built that doesn't distinguish between its main memory and its mass storage. The two functions would be served by the same solid state circuitry. Obviously accommodating such a hardware design would give the kernel guys fits, but it could simplify things in the software a great deal, and incidentally net an interesting performance gain that's visible to users. Notably, the process of launching a program consists of nothing more than creating a stack and a heap for it somewhere--the program's code can stay right where it is. This also results in the somewhat bizarre (to modern ears) situation where suspend mode consists solely of persisting the CPU's state. Memory state is already persistent, always. As a final side effect, once scaled to SSD capacities, a device operating as described above effectively has an absolutely absurd amount of main memory, in theory, equivalent to the entire remaining capacity of the mass storage device.
MRAM has been around in labs for 20 years now, so the possibility of this being a real, viable, product-ready device is reasonably high. MRAM doesn't suffer from Fusion Power Syndrome.
It has much higher performance flash and persistence but at a big cost in size, power and money. I think this sounds like good case for using it as write cache for SSDs that you don't need to flush. Imagine for example a log file that's very volatile, a line gets written every few seconds. Or that document or spreadsheet or email you're working on that Office auto-saves all the time or game autosaves for that matter. With this you could commit it to MRAM and it'd be written "for real" even in case of power failure with no supercap to flush to NAND without wasting write cycles on it. They say a 50:1 cost compared to NAND so on a 256 GB SSD a 512 MB cache should add ~10% to the cost.
If you only need to push the most stale writes to NAND you could download a 50MB installer, install it using 100MB writes then delete the installer and it'd never need to touch the NAND at all - it's marked free again before it's ever written to disk once. Oh yes and you'd also get better burst IOPS as a bonus. If it really can't be worn out like RAM that is going to be huge, even if it just comes on top of the technology we already have and doesn't replace anything. After all, most of my SSD is the same from day to day - the "active set" that gets written to is much smaller.
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We're not too far away from the ultimate limit of smallness on all semiconductor technologies: single atom scale. Flash will stop improving then. More importantly, flash has two important defects: slow write time and an inherent wearout mechanism. So the ultimate (i.e.30 year) question is "can magnetic RAM cells be economically made about the same size as flash?" If the answer is yes, flash becomes obsolete.
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It can actually replace both, which is pretty interesting and might change how our current computing model is built.
There are already applications and systems in place to model the data storage like this, for example memory-mapped file I/O, where you basically tell the operating system that "please let me pretend that this huge file on the hard drive is already in RAM", and let the RAM be some sort of huge cache. The same model would apply to storage here, except we would get rid of the whole RAM layer between storage and CPU.
c++;
Everspin previously used the crossed-lines writing technique (shown here http://thefutureofthings.com/upload/image/articles/2006/mram/mram-write.jpg), but has now switched to spin-transfer torque based devices. Several other companies are also working on this, so things to improve rapidly. PR release at (http://www.engadget.com/2012/11/14/everspin-throws-first-st-mram-chips-down/)
Yes, but many existing silicon technologies are running up to lots of hurdles right now at current feature sizes, so the single atom problem isn't close to being a concern. Some of the newer technologies not only allow much smaller feature sizes than the current 20nm, but will also allow stacking of components, rather than having a single layer of components as we do now in chips. Not only that, but some are non-volatile, yet fast enough to replace DRAM, so they would have a greater market being able to provide both ram and storage solutions. Hopefully that greater market combined with increased densities will lend itself to greater production and economy of scale. Who really knows though, there may be limits to how much they can produce, and thus the greater market will instead cause them to be priced at a premium. I'm just gonna wait and see, and be hopeful.
Everspin has announced that it's shipping the first 64Mb ST-MRAM in a DDR3-compatible module. These modules transfer data at DDR3-1600 clock rates, but access latencies are much lower than flash RAM, promising an overall 500x performance increase over conventional NAND.
Wait, so, is this to replace RAM (the mention of DDR3) or to replace drive storage?
MRAM might be a potential candidate to replace current solid state storage (NAND-flash) which is a candiate to replace drive storage. In a system with small amounts of DRAM, MRAM might be used to replace the DRAM as well. Unfortunatly, because of its current high price and low density, it is currently not very good substitute for either one except in perhaps a very small embedded system.
These modules transfer data at DDR3-1600 clock rates, but access latencies are much lower than flash RAM
Isn't that comparing apples (DDR3) and oranges (flash RAM)?
Instead of implementing the slow standard flash memory electrical interface on MRAMs, they (everspin) elected to support the same fast electrical interface that DRAMs use (DDR3). They can do this because just like DRAM, writing data on MRAMs is about as quick as reading data (which isn't the case with NAND-flash). By choosing the standarized DDR3 interface, chips that might want to use these MRAMs won't have to be specially designed to do so (which wouldn't be the case if they came up with a non-standard interface). It will apparantly just look like a small capacity DRAM chip that doesn't forget when you take the power away (I'm guessing the MRAMs probably also ignore any refresh requests that come across the interface).
The reason that current flash memory electrical interfaces are slow, is that flash memories have pretty slow access times and are read/written in large blocks. This led to an efficient interface that multiplexes the address and data on the same pins. DRAM is however more randomly accessed in smaller blocks and has separate address and data pins. This allows a higher duty cycle of data transfer on the data pins for smaller transactions: you don't have to constantly turn the bus around between sending commands and reading data, and you can pipeline new addresses on the address bus at the same time data from older commands are transfered on the data bus.
By targetting the DRAM interface, it appears that Everspin is positioning their chip as a DRAM+Flash replacement for systems that don't require much total storage. They need to target the DRAM interface for this because you can't really do random access efficiently on the flash interfaces (but you can do block transactions on a random access interface). In fact in many embedded systems, the first action of the bootstrap code is to copy parts of the NAND into DRAM (for fast access). With MRAM, you could just bypass this step.
Some of the newer technologies not only allow much smaller feature sizes than the current 20nm, but will also allow stacking of components
Sure we can stack them, but can we cool them? Even the Ivy Bridge chips that lowered power consumption a lot compared to Sandy Bridge increased the watt per mm^2 die size due to the die shrink and now it's up to 77/160 = 0,48 W/mm^2. That is a lot of power you have to dissapate to keep a sane operating temperature. Having a flat chip - ignoring the 3D transistors, which are practically flat for this purpose - connected to a huge heat sink is a pretty effective way of doing that. If you stack the chips many of them won't be on the outside. First they have to transfer all the heat through the other layers, then to the heat sink. Supercomputers have worked on it for decades and they haven't really found a working solution.
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