Moore's Law Fails At NAND Flash Node

An anonymous reader writes "SanDisk sampling its 1Y-based NAND flash memory products and has revealed they are manufactured at same minimum geometry as the 1X generation: 19 nm. The author speculates that this is one of the first instances of a Moore's Law 'fail' since the self-fulfilling prophecy was made in 1965 — but that it won't be the last."

Comments

It has not failed yet

[Anonymous Coward]

Moore's Law applies to the number of transistors in a chip. Just because you have found an increase in performance that did follow Moore's Law for a while does not mean that Moore's Law is somehow about flash memory. Therefore, when the increase no longer follows Moore's Law, it does NOT mean that Moore's Law has failed. The only thing that has failed is your own prediction that things other than the number of transistors would follow that curve.

Re:It has not failed yet

[tlhIngan]

Moore's Law applies to the number of transistors in a chip. Just because you have found an increase in performance that did follow Moore's Law for a while does not mean that Moore's Law is somehow about flash memory. Therefore, when the increase no longer follows Moore's Law, it does NOT mean that Moore's Law has failed. The only thing that has failed is your own prediction that things other than the number of transistors would follow that curve.

And transistors (even floating gate ones - they're just transistors with an extra gate not attached to anything) has a strong correlation with capacity.

There are two kinds of ICs out there - pin-limited and area-limited. Pin limited ICs are your SoCs and CPUs and such - where the functionality of the entire chip is limited entirely by the number of I/O pads you can stuff on the die and the package while still maintaining adequate yields (the more I/O pads, the more chance of failure during bonding to the package - so while the silicon die may work fine, the attachment to the package didn't).

Area limited ICs are the opposite - these are where their functionality is limited purely by silicon area. The problem with making a die too big is the increased likelihood of failure caused by wafer imperfections, which decreases yields. As each wafer has a fixed area, a bigger die also reduces the number of ICs you can make from it. So bigger dies lead to lower yields due to imperfections and lower yields due to being able to make less per wafer (the fixed cost is actually pretty large compared to the processing costs).

Area-limited ICs include camera sensors (you want bigger sensors, but bigger sensors translate directly into lower yields as the sensor matrix has more imperfections ("dead pixels"), lower yields (bad sensors with too many bad pixels, and lower numbers of sensors per wafer), an higher costs (which is why a full-frame dSLR costs way more than one with an APS-sized sensor). Likewise, memory products are also area limited - because if you can use more die area, you can have a larger device. But too large means your high-cap dies are low yields and thus high prices. So to solve this, smaller transistors mean you can pack double the transistors in the same area (per Moore's law) and have practically twice the storage.

An area-limited IC tends to be very transistor-dense. A pin-limited IC tends to have hotspots of transistor density (embedded memories like caches) which comprise the vast majorities of transistors in a chip, but for the most part, what takes up space on pin-limited ICs is wiring. So much so that wiring tends to be the one spreading transistors out and making them less dense.

Re:It has not failed yet

[Lunix Nutcase]

Moore's law which states that computing power (not necessarily transistors) will double every 18 months.

Wrong. This is what Moore actually said:

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.

Notice how it says nothing about "computing power".

self-fulfilling prophecy?

[fredrated]

I don't think the summary writer knows what that means.

Journalist Wanted Moore Hits

[neoshroom]

From the article: Some might argue that the die area saving achieved is equivalent to a process node move, and that as Moore's talked about the number of transistors per IC his law is not dependent on a reducing minimum geometries. I think that most will see that this runs against the "spirit" of Moore's Law.

From Wikipedia: Moore's law is the observation that, over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years.

From article linked off the main article: SanDisk has now revealed that 1Y – now described as a generation rather than a node - is the company's second generation at 19-nm. What the company does claim to have achieved is a reduction in the memory cell size from 19-nm by 26-nm to 19-nm by 19.5-nm, delivering a 25 percent reduction of the memory cell area.

So, if you can fit more cells using the same size process, it doesn't go against the spirit or the letter of Moore's law. Moore's law is about computing power. If you get more computing power without reducing size to do it, that still counts.

Re:NAND flash = transistors on a chip

[msauve]

It's not just "transistors on a chip." It's a very special type of transistor which is able to store a charge while unpowered. You'll find that Moore's law doesn't apply to power transistors, either - there are fundamental constraints on size due to the need to handle high current.

It's unreasonable to claim that Moore's law applies to special cases.