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Intel Launches Core I7-4960X Flagship CPU
MojoKid writes "Low-power parts for hand-held devices may be all the rage right now, but today Intel is taking the wraps off a new high-end desktop processor with the official unveiling of its Ivy Bridge-E microarchitecture. The Core i7-4960X Extreme Edition processor is the flagship product in Intel's initial line-up of Ivy Bridge-E based CPUs. The chip is manufactured using Intel's 22nm process node and features roughly 1.86 billion transistors, with a die size of approximately 257mm square. That's about 410 million fewer transistors and a 41 percent smaller die than Intel's previous gen Sandy Bridge-E CPU. The Ivy Bridge-E microarchitecture features up to 6 active execution cores that can each process two threads simultaneously, for support of a total of 12 threads, and they're designed for Intel's LGA 2011 socket. Intel's Core i7-4960X Extreme Edition processor has a base clock frequency of 3.6GHz with a maximum Turbo frequency of 4GHz. It is easily the fastest desktop processor Intel has released to date when tasked with highly-threaded workloads or when its massive amount of cache comes into play in applications like 3D rendering, ray tracing, and gaming. However, assuming similar clock speeds, Intel's newer Haswell microarchitecture employed in the recently released Core i7-4770K (and other 4th Gen Core processors) offers somewhat better single-core performance."
"a die size of approximately 257mm square."
I suspect that should be 257 square mm. A 257 mm square die couldn't even be covered by a standard sheet of paper (US:letter, EU:A4)
"National Security is the chief cause of national insecurity." - Celine's First Law
Amazing. Everything you said about HT is completely wrong. Where ever did you get this information?
Intel's hyperthreading consists of two logical processors sharing the same compute resources. Each logical processor has its own register set but shares decoders, adders, shifters, cache, etc. as it goes about executing its assigned thread. The sharing process is vastly more complex and efficient than you seem to think -- there's no alternating of cycles. Once instructions are decoded into uops, they flow through the pipeline in a dynamic fashion that sometimes leads to one thread using most of the resources while the other one waits. In fact, this is a big advantage of the design -- when one thread stalls from a cache miss, the other one uses all the resources until the first thread's memory access completes. A much better plan than your scheme of using only even/odd cycles.
Managing this process is not simple, and steps must be taken to avoid both deadlocks and livelocks as the two threads compete for resources. But the process is dynamic -- the design allows one thread to run unimpeded when it makes sense to do so, while still preventing one thread from being starved at the other's expense. But this "every other cycle" notion of yours is pure nonsense. The core can retire up to four uops per cycle, and at times these all come from the same thread.