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Imagination Tech Announces MIPS-based 'Warrior P-Class' CPU Core
MojoKid writes "Imagination Technologies has announced the first CPU based on its new version of the MIPS architecture. The new P5600 chip (codenamed Warrior) is a 32-bit CPU based on the MIPS Series 5 architecture and is designed to challenge companies like ARM in the embedded and mobile markets. Major features of the new chip include: support for 40-bit memory extensions, or up to 1TB of RAM, a 128-bit SIMD engine (Single Instruction, Multiple Data), and Hardware virtualization (MIPS R5 can virtualize other machines in hardware). The P5600 core is being touted as supporting up to six cores in a cache-coherent link, most likely similar to ARM's CCI-400. According to IT, the chip is capable of executing 3.5 DMIPs/MHz in CoreMark, which theoretically puts the P5600 on par with the Cortex-A15."
That's a bit dated, isn't it?
COMPETITION IS GOOD.
I'd love to see MIPS make a comeback. I've been looking for one of the looongson (?) netbooks for awhile now, just so I can have a MIPS Linux box to play with, but those seem hard to come by.
If you were me, you'd be good lookin'. - six string samurai
It all sounds great, but if consumes more power than similar performance ARM SoCs then what's the point?
That is a bit strange to count Integer operations. Most of the computations one do nowadays are mostly floating point. Also,there is no mention of memory bandiwdth and cache size. Though I'll stay tuned.
You can still find plenty of MIPS based embedded cpus but they're getting more and more obscure.
One of my very favorite things about the "smartphone revolution" is the proliferation of cheap ARM based SoCs. For a couple of bucks you can get a complete system in a package that runs on a couple of watts and runs circles around a high end workstation from a decade ago. (It's hard to belive 2003 was a decade ago.) And these aren't crippled micros. They're complete systems that run a real full fat operating system. Just look at the raspberry pi. Memory management On package DDR memory. Frame buffer with openGL aclleration and hardware video decoding. Amazing stuff.
Point is, arm is everywher, easy, and cheap. What's the benefit of going MIPS? (Or SH3, or PPC..)
I hate to sound like Richard, but Imagination Technologies has a horrible track record when it comes to even supporting Linux let alone supporting open source. MIPS was better off dead.
Can it run IRIX?
The headline doesn't say, but this chip is based on the MIPS Technologies ProAptiv fully synthesizable core, which has the highest Coremark score/area. Note the Coremark score is not representative of a processors performance as that is largely limited by the attached memory hierarchy, which is not measured by Coremark. In modern CPUs the core uses less than 10% and in some cases less than 1% of the power and area of a chip, so the design of the memory hierarchy, particularly the L2 and L3 cache, and how they handle contention is far mroe important.
Chips based on this new Core are a ways out.
We've seen this before. Imagination blown to bits in the PC 3D-accelerator marketplace, and forced to withdraw with its tail between its legs. Now Imagination seems on the edge of admitting defeat in the hight-end ARM GPU market, and vanishing into this fantasy market of competing with ARM using its MIPS core.
The problem Imagination has is that there are too many players in the ARM GPU space. ARM itself provides MALI cores, both cheap and nasty ones for all bottom end ARM SoC devices, and high-end ones for GPGPU applications. Qualcomm, of course, has the Adreno (via a long ago purchase of ATI's mobile GPU division), and Qualcomm is the current 'Intel' of the ARM market. Nvidia and AMD are both providing their AAA gaming/GPGPU cores to 2014 ARM parts, moving the ARM high-end beyond anything Imagination can dream of matching.
At the moment, PowerVR is 3DFX (at the height of its success) strong in the ARM market, but faces the same problems that brought 3DFX's fortunes crashing down. PowerVR is currently used by Apple in all its non-x86 products. The important Chinese ARM chip companies are also starting to use PowerVR as well. PowerVR is in a golden age, but struggles to see a sunny future.
Soon, basic OpenGL ES2.0 functionality on ARM SoC parts will return almost worthless to the GPU IP companies. Good enough acceleration for everything but proper games (which have yet to have an important impact on ARM devices) is in a hardware race-to-the-bottom, with too many excellent competing designs. This mirrors the end of value in the PC 2D video space, after years of excellent profit for companies like Hercules, S3 and Number-nine.
No-one survived against AMD/ATI and Nvidia in the AAA-gaming GPU space. AMD won the Wii U, PS4 and Xbone. The existing handhelds are the last bastion of non-Nvidia, non-AMD GPU designs for proper gaming. AMD and Nvidia have worked hard recently to scale their desktop solutions into the high-end of the ARM mobile space, and intend to provide no-compromise gaming GPUs for this market.
The last time Imagination went up against Nvidia and AMD, it was a bloodbath, and both companies are far better and far more ruthless today.
So, now Imagination is biting the hand that feeds it- namely ARM. You can imagine how this will end. And Imagination is throwing their hat into a ring where Intel fights (with ZERO success). If Intel cannot beat ARM (and it most certainly cannot), Intel can take some pointless satisfaction in pummelling Imagination's MIPS ambition into non-existence. Wherever Imagination takes MIPS, it will find Intel there first with 'Quark' and other assorted Intel rubbish that Intel has the money to persuade companies to use ahead of anything but ARM.
Odds on there being any open source drivers for this SoC? ImgTec is known for being hostile towards open source in general and delivering shit-grade binary-blob drivers that perform poorly and are rife with compatibility issues.
MIPS are for kids!
Take the cheese to sickbay, the doctor should see it as soon as possible - B'Elanna Torres, "Learning Curve"
Many of the MOST POPULAR dd-wrt systems are MIPS based
... designed to challenge companies like ARM in the embedded and mobile markets. ...
Major features of the new chip include: support for 40-bit memory extensions, or up to 1TB of RAM, a 128-bit SIMD engine (Single Instruction, Multiple Data), and Hardware virtualization (MIPS R5 can virtualize other machines in hardware). The P5600 core is being touted as supporting up to six cores in a cache-coherent link, most likely similar to ARM's CCI-400. According to IT, the chip is capable of executing 3.5 DMIPs/MHz in CoreMark...
hmm... seems a bit limited for a smartphone processor.
Anons need not reply. Questions end with a question mark.
Precisely!!! At this day & age, if your 32-bit CPU requires 40-bit memory extensions, then why bother making it 32-bit? Particularly when the architecture in question - the MIPS - has by now mature 64-bit implementations in MIPS IV & V? Incidentally, what do they mean by Series 5? MIPS V, if that's what they mean, is a 64-bit CPU - starting from the R10k onwards.
I recall in the early 90s, when some companies such as QED & IDT did CPUs like the R4600: that would have been a fine template to start from in making this one. Which also brings up the question - what's the target application? If it is tablets/cellphones, then even that market is already headed towards 64-bit, w/ the iPhone already there, and probably Android & Windows Phone next.
Looking back @ things, MIPS would have been the perfect platform for Microsoft, given what it does today. It was 64-bit (R4k) when NT debuted, and it was one of the platforms supported by CE. It has been low powered, and popular in routers & other networking gear. Had Microsoft consistently supported that platform on NT & CE, then they could have done something like Windows 8 a lot earlier than they did, at least as far as phones & tablets went.
Imagination will continue to thrive as long as Apple thrives
I wouldn't bet on that, Apple have been building a GPU team for a while now.
And where to we get 1 TB of ram? For consumer use - good luck.
Does it run angry birds?
The P5600 core is being touted as supporting up to six cores in a cache-coherent link, most likely similar to ARM's CCI-400.
The CCI-400 is not relevant here. In both MIPS and ARM worlds CPUs are now multi cores capable out of the box. One cluster can be configured from 1 to 4 cores typically, and here for this latest MIPS up to 6. The L2 management is handled as part of the cluster, which also typically supports coherency with external hardware accessing the L2 through one or several coherency port(s). The L1 cache(s), the L2 and the hardware are kept coherent inside a cluster (with some limitations at times on the low end, there are variants). All this can be taken for granted at the high-end, as here.
Now what the CCI-400 does is different: it extends coherency management between several clusters. This is very important in the ARM world because of the big.LITTLE scheme: you want the big cluster and little cluster to be kept coherent to speed-up and easy the transition between the low-power and high performance modes (that also helps when all cores are used at all times, as the OS can migrate tasks between cores more efficiently).
MIPS provides a much cleaner upgrade path going forward than ARM. MIPS64 is a very clean extension to MIPS32. All of the MIPS32 instructions behave the same except that they are sign extended to 64-bit. 64-bit ARM on the other hand has almost nothing in common with ARM32. The instruction encoding is totally different. The register definitions are also completely different. A lot of the things that made ARM ARM are gone such as conditional execution.
I have spent many years working with MIPS and the last three working for a 64-bit multi-core MIPS manufacturer. MIPS also allows for clean extensions to the instruction set by various vendors, something ARM does not allow. For example, my employer has added a lot of instructions using coprocessor 2 (COP2) to add encryption, hashing, CRCs and more without breaking standard MIPS compatibility since COP2 is typically reserved for vendor extensions.
MIPS page tables are also interesting. They are entirely managed by software, allowing the operating system to use whatever format they want for them. While some vendors have added hardware walkers they typically don't make much difference in performance.
MIPS32 is fairly old and many implementations don't provide cache coherency which is a pain in the butt and impacts performance but the ones I deal with (Cavium's OCTEON processors) are fully cache coherent.
As for doing encryption in the instruction set it allows full acceleration in user space without needing to deal with descriptors or DMA or userkernel transitions.
Perhaps the only thing I would get rid of is the branch delay slot. It no longer really buys anything. The MIPS tools are much more mature than ARM, especially for 64-bit support. There are 32 general purpose registers with register 0 always being 0.
With ARM64 most of the interesting ARM features are gone and in fact it looks a lot more like MIPS except that the instruction decoding is a lot more complicated. MIPS hasn't been standing still either. Extensions have been added for things like virtualization, 16-bit instructions (like Thumb) which usually don't buy you much and some multimedia extensions.
I periodically work on MIPS assembly language with some of the bootloader stuff I do. All I can say is it's a joy to work with compared to X86 and is quite elegant. It's nice when I can have just a couple dozen lines of assembly language put a stack in cache memory and go straight to 64-bit C code. At this point it's quite hard for me to beat recent versions of GCC when it comes to optimizing code.
I don't know why they're limiting their Warrior P-Class CPU core to 32-bits though. Moving to 64-bit MIPS is not very difficult. Personally I'd love to see 32-bit MIPS go away and just do 64-bit MIPS and use either the N32 or N64 ABI. N32 runs in 64-bit mode but with 32-bit addressing so you get all the advantages of 32-bit pointers and 64-bit registers.
My employer makes MIPS processors with up to 32 cores and soon will have 48 cores and fully support Linux.
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It's about time for a competitive MIPS mobile processor. The relatively open architecture is so well-supported by so many different operating systems for decades. I'm glad to see the modernization of MIPS32 as well as the MIPS64 Chinese Loongson supercomputing initiative.
Kriston
Yet nobody has gone w/ an embedded SPARC. Think of the advantages - SPARC had a rich host of applications, and could run not just Solaris, but Linux & OpenBSD as well. So if something like, say, Scientific Linux, were ported to it, it would be the perfect engineering workstation out there. Yet, SPARC ultimately lost all that first to RH/PCs, and later to Wintel. W/ the result that it has no niche even there anymore.
The companies that used to make SPARCS are either dead (Ross Technologies) or abandoned it (Cypress). Who else makes them?