Intel's 14nm Broadwell Delayed Because of Low Yield
judgecorp writes "Intel has put back the delivery of its 14nm Broadwell desktop chip by a quarter because of a manufacturing issue that leaves it with too high a density of defects. The problem has been fixed, says CEO Brian Krzanich, who says, 'This happens sometimes in development phases.'"
The good news is that it is just a defect density issue. A first round of tweaks failed to increase yield, but Intel seems to think a few more improvements to the 14nm process will result in acceptable yield.
14 nanometers should be enough for anyone.
Really - why do we keep shrinking these things. 640nm chips worked just fine and probably had fewer defects.
Short term setback for Intel. They will get yield up eventually. I just hope it's before they run out of cash to run operations...
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I have always been told size doesn't matter!
Since, in practice, they'd want to get rid of old stock before selling their shiny new product, this isn't really that much of a problem.
It's not like AMD is going to magically beat Haswell before Broadwell is released. It would be nice if they did, though...
I just hope it's before they run out of cash to run operations...
Lolwut? Yeah, umm, that's not even remotely a concern.
... where does it end? I had to actually check what the atomic size of Silicon is (111pm), so there are only a few years left (maybe 10-20) to reach the atomic level. Then what? I'm really curios as I'm quite impressed how this development came - actually how quick...
Sorry, tongue was firmly in cheek on that one..
"File to fit, pound to insert, paint to match" - Aircraft Maintenance 101
On the other hand, the guys at Altera have bet the bank on Intel, so they're likely praying that Xilinx's 16nm TSMC process gets delayed.
While Intel has utter dominance on their market, Altera is in catch-up mode...
They released Haswell in June, they've barely had time to sell that so Q4 2013 to Q1 2014 is still ahead of their yearly tick-tock. They're not announcing any delay to Airmont which is their mobile 14nm chip and we all know one quarter to or from won't change much in the desktop/server market. In related news AMD posted their Q3 earnings today and their CPU sales are still down, their gross margin is down but on the bright side the console sales are finally coming in so overall they're making a profit this quarter. Inventory is way up but I hope that is due to build up before the PS4/XBone launch, what disturbs me is that their R&D is still going down. That's a death spiral in the CPU/GPU/APU business.
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Intel has produced two new generations of processor that were WORSE than Sandybridge. Higher power use (under load) and far less over-clockability. The newer part were ONLY better (in desktop systems) if you intended to use their new instructions (vanishingly unlikely) or the integrated graphics (which would be pointless- people buy expensive Intel CPUs to partner them with expensive GPUs from AMD or Nvidia).
Intel, of course, were in the same position with the waves of Core2 parts, each of which essentially overlapped each other in performance generation on generation (although power consumption was much improved over the first generation of Core2 i7 parts).
Intel currently doesn't know exactly where to go in the near future, and is attempting to hedge its bets by trying various things. It is currently undercutting its own HYPER-expensive ULV mobile high-end parts with the new 4-core 'atom' Bay-trail chips that seek to go head-to-head with ARM. Because current high-end ARM is so good, Intel is forced to sell a very dangerously good chip (dangerous to Intel's profits, that is) into low and mid-end tablets, running Android or Windows8.1
However, even Intel's first decent 'Atom' part ever (after 5+ attempts) is beaten by Nvidia's somewhat lame Tegra 4, and Qualcomm's Snapdragon 800. It is exterminated by Apple's new ARM chip, soon to be seen in Apple's new iPad refresh.
Intel's 22nm process, and use of FinFETs, has been a total disaster so far. A process advantage, and custom designed chips, doesn't allow Intel to beat ARM parts coming from commodity foundries at TSMC and Samsung in 28nm. Sure, Intel can make its own chips smaller than those on the previous process, and theoretically get more parts per wafer, but the per wafer costs rocket, the yields drop (initially), and insanely expensive new plants have to be built to service the new process.
What does Intel get from spending all this new money on R+D? At this moment in computer history, almost nothing. The x86 is dying, and everyone BUT Intel builds ARM solutions. Every major player has a GPU (graphics) solution as good as Intel, and Intel isn't within a million miles of matching the AAA-gaming GPU designs from AMD and Nvidia (despite the fact that Intel has spent more money than every graphics company combined, across their combined periods of existence, to create its own GPU solutions).
Intel simply has no current use for its expensive 14nm process. It has built the factories, so it is engaged in a waiting game- waiting for mobile parts to roll off the 14nm production lines that have clear market advantages over its current mobile chips. It just isn't worth Intel's time launching another round of non-improved parts. The market has changed forever, and on-one wants to buy "this season's Intel" for the brand loyalty reasons previously apparent.
Intel fanboys want 6-core and 8-core parts, but Intel is extremely loathe to risk introducing better value into the desktop market. If Intel properly sold 6-core solutions, they would have to sell 6-core i5 parts, and these would beat-up their EXTREMELY profitable 4-core i7 parts. Intel is too in love with the status quo.
If Intel's bay-trail 4-core parts prove good enough for tablets and non-gaming laptops, and they will do having greater performance than the more than adequate mobile 2-core core2 parts used in the first decent cheap laptops years ago, where does most of Intel's mobile biz go from here? Bay-trail parts (unlike those years old mobile 2-core core1/core2 laptop chips) also do all the video decoding in hardware, allowing flawless playback of all current video content (and bay-trail is strong enough to do CPU enhanced decode of 4K video recorded in h264).
Bay-trail is the part Intel moved Heaven and Earth NOT to produce. Bay-trail is the final step on the race-to-the-bottom for x86 based computers that most non-AAA gamers will need. If the only real money Intel makes ends up from chips lie Bay-trail, Intel is done.
Think about this. In a few weeks, you
So make a "triple core" edition called an i4 where really 1 core just didn't pass quality control so they turn it off. AMD did it and it sold so well they had to purposely cripple working quad cores to meet the demand for triple core chips.
I have a theory that those T-edition chips Intel made that are just underclocked, hyper-efficient, ultra-low wattage editions of their recent chips are actually just ones that wouldn't run properly at the normal stock clock. I never heard a solid claim that they actually had different voltage regulation circuits or something like that. They just underclocked them and made them have a higher tendency to not click to a full multiplier level as often or for as long.
Might explain why I went with an AMD processor, and might get a video card from them soon.
'I like my chips like my women: hot and slow.'
And what kind of problem you can have on a fab that is not a "defect density issue"?
In a related question, can I declare Moore's law dead already, or is there some current fab upgrade that isn't delayed by at least 18 months?
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If you reduce all 3 dimensions of a wire by the same proportion, you'll get a wire with highter resistance, not lower. The energy savings from reducing the feature sizes come from reducing transistors and inter-wire capacitance. With a smaller capacitance, you need less charge to turn the transistors on or off, using less power and letting them switch faster.
That is, untill you let too much current leak through them. Make them too small, and you'll consume more power again.
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You want a good "cpu" not using too much power, not creating too much heat and fair price.
At this point in time Intel on the desktop covers more of the first three aspects.
If Intel goes for a more mobile offering for a few generations, AMD will be back in consideration.
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... because of a manufacturing issue that leaves it with too high a density of defects.
Sorry, after a long time, I have to put myGrammar Nazi hat on for (I think) the first time. It's not just you, this is just the example that tipped me over the edge - much like the "leaves it with too high [of] a" phrasing leaves the reader tipping off into.... what?
This type of construction has become endemic in conversation in the last few years, and I'm sorry, but it's cumbersome, ungainly, unsightly, and painful to hear or see. Perhaps, just perhaps, if I say something, this bad practice will lose some momentum and die out.
I would like to suggest to everyone who uses this "too high of X" construction, to consider using something more like this: "... leaves it with a defect density that is too high." See, that flows, it keeps the primary objective phrase (leaves it with a defect density) nicely collected, with the modifying phrase (that is too high) also nicely collected. IANA GN to the point of recognizing if the problem is a split infinitive or other formal error, but I know the original is bad.
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16nm has the same wire pitch as 20nm so it's not much smaller than Intel's 22nm.
Lower yields are also not an enormous problem for FPGAs, you can ship with some gates disabled.
TSMC's metal 1 pitch is 64nm in 20nm, and Intel's 22nm is 90nm.
14/16 is indeed expected to have ~64nm pitch, so it's not better than TSMC's 20, but it's a great leap for Intel.
"disabled": Not quite. When I'm running 491MHz internal, you can't just disable arbitrary logic on me. The slower parts may get away with disabling columns, but you can't change my timing without breaking my design.
Also, all the hard IP is not redundant, and there's more and more of it.
"disabled": Not quite. When I'm running 491MHz internal, you can't just disable arbitrary logic on me. The slower parts may get away with disabling columns, but you can't change my timing without breaking my design.
This, this, this. And I tend to doubt anybody is even trying to improve yields in slow grades that way. FPGAs need every possible path to be predictable, from data files distributed with the tools. It's not just about setup time -- variability in hold time can be really nasty for timing closure, and hold time violations can't be resolved by reducing clock speed.
On the Xilinx side, the only yield game I know of is their pseudo-ASIC program offered to volume buyers of large-die parts. You prototype using normal fully functional chips. Once you're ready for production, you supply them with your final bitfile and they handcraft a test program which tests only the fabric resources you're using. This can dramatically improve yield for a large part, allowing them to offer substantially lower prices. You get one mulligan if you need an ECO (and presumably no guarantees that the parts they've already shipped to you will pass the new test vector).
For small-die parts they don't even bother with that stuff.