ARM Researching Novel Chip Memory
An anonymous reader writes "ARM may be best known as processor designer but the company is now working on a non-volatile memory that could scale down to 5nm, according to an Electronics 360 report. The memory is something different called Correlated-electron RAM that was originally developed by a professor at University of Colorado. ARM is joining a research collaboration to try and make the memory an option at ARM-friendly foundries."
I love that ARM didn't initially go head to head with Intel and thus ended up not getting crushed by them (think transmeta/AMD). I thus have hopes that this not only works because it is cool but because ARM is cool and deserves another win for what they have done.
efficient SRAM would be a bigger deal. DRAM is holding us back right now.
gotta love you ARM fanboys, as misguided as you are.
ARM's days are numbered. It can try to come up with whatever hacks it wants, but in the end, they can't beat physics. And if anyone understands that, it's Intel. MIPS won't change that. So prepare to watch ARM flail around while it loses significant market share to Intel over the next year.
As for Nvidia... they love to overhype and underdeliver in hopes people will just settle for what they're offered. Nvidia will partake in the same woes as ARM over the next year, too.
The only winner in this game is Intel. They have the know-how, fabs, and process perfected. They also have the gameplan mapped out. They're no idiots.
Except that 16/14nm isn't much more logic dense than 22/20nm. Now we keep making the minimum feature size smaller, but the gate length is about the same size (e.g, FinFet). Of course types of circuits scale better than others (e.g. rams), but one of the reasons to not scale down is that power wall (it's currently better to have larger devices to minimize static current leakage than have minimum sized devices and melt the silicon as soon as you turn it on).
At 10nm, quantum tunnelling is a significant impediment to low power operation and there is no established way to bring it to market-level yield (immersion lithography and multi-patterning yield isn't really panning out as well as people have hoped for random logic). We will probably no-doubt see memory devices at 10nm in a year or two, but random logic doesn't seem to be in the cards for a couple years at best, and the original poster may be correct, it may never reach economic sense to use it (if they can't get the leakage under control and it gives about the same random logic density when you use low leakage, larger logic gates) vs a previous more mature 14nm node.
Intel likes it because their CPU chips are mostly L2/L3 cache rams so they are willing to pay the cost penalty of using a new node, but it may not make sense for others to follow. Even Intel is hedging their bets with larger wafer sizes in their next generation fab to get more production efficiency through the flow rather than totally betting a smaller die size from a smaller geometry process...