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Will 7nm and 5nm CPU Process Tech Really Happen?
An anonymous reader writes "This article provides a technical look at the challenges in scaling chip production ever downward in the semiconductor industry. Chips based on a 22nm process are running in consumer devices around the world, and 14nm development is well underway. But as we approach 10nm, 7nm, and 5nm, the low-hanging fruit disappears, and several fundamental components need huge technological advancement to be built. Quoting: "In the near term, the leading-edge chip roadmap looks clear. Chips based on today's finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture. ... The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec's CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source. ... By 7nm, the industry may require both EUV and multiple patterning. 'At 7nm, we need layers down to a pitch of about 21nm,' said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. 'That's already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it's going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.'"
Clearly e-beam has some serious issues (throughput, to name one...), but progress is being made on that front. For instance, http://www.mapperlithography.c... ( http://nl.wikipedia.org/wiki/M... -- though it appears there's only a Dutch entry...).
We're already at the point where 22nm components are more expensive per transistor than those at 28nm.
Previous shrinks lowered the cost of each transistor. It doesn't look like it's going to happen after 28nm.
Kind of. Heat dissipation starts being a bigger problem, and thermally limit slock speed. Look at overclocking sandy bridge vs ivy bridge chips.
You'd think so, but the problem is global interconnect. Not gates. It was all the way back at the 250nm node when interconnect and gate delay were about the same.
At the 28nm node, wire delay is responsible for something like 80% of the time it takes for signals to work their way through a circuit.
And it some cases inverters are actually used to help signals propagate more quickly down long wires. In other words, long wires are so slow compared to gates that adding gates can speed things up!
I remember the 90's too and I don't remember any of that.
The race to 1 GHz were heady, optimistic days, and I don't recall anyone thinking that once we got there, it would all be over.
So I call bullshit on your post.