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Parallax Completes Open Hardware Vision With Open Source CPU
First time accepted submitter PotatoHead (12771) writes "This is a big win for Open Hardware Proponents! The Parallax Propeller Microcontroller VERILOG code was released today, and it's complete! Everything you need to run Open Code on an Open CPU design. This matters because you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to its source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design."
I run a company that releases all its hardware designs and am a huge proponent of OSHW. This gesture has limited utility simply because the people who use MCUs in designs aren't typically interested in delving into the minutiae of how the processor that runs the system is built. They're more interested in open source circuits which have real-world applications -- a low pass filter for smoothing PWM signals, a nice clean USB power supply, and so on.
Aside from absolutists positions like Stallman's, why is it important to have OS hardware? Why AMD64, Intel x86, or ARM is not good enough?
I wonder how this CPU performs? Does it compare to anything I'd care about ...?
The Parallax Propeller CPU is mainly used for hard realtime applications. It has eight 32-bit cores (called "cogs"), each with 2k of dedicated memory, and 32k or shared memory. Each cog runs at 20 MIPS. That is not nearly enough speed or memory for any sort of general computing, but is enough for control loops in embedded systems. The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.
So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.
Here's an open FPGA design:
Put a buttload of OR gates in parallel.
Follow them with a buttload of AND gates
There just isn't that much design in a basic FPGA to open up, not that I can see.
Said the blind man.. What you describe is the end user description of a PAL. FPGA's are completely different and PALs are not actually designed that way either. It is just the end user description, much like knowing the x86 instruction set doesn't mean you know how to design a modern x86 processor.
An Altera or Xillinx FPGA is predominately a sea of small SRAM's but there are also many many muxes, complicated interconnects, configurable special function blocks (like multiply/accumulators, IO cells, and Ethernet interfaces). There is also a great deal of logic just to efficiently move configuration bitstreams into the chip. The complexity per unit area is less than a typical ASIC, which makes FPGA's good subjects for bringing up on new process flows but it is definitely not trivial work. Much is low level and structural rather than logical but that doesn't make it easy.
That said, an open FPGA design would be pretty useless. The hardest part is that low level process dependent optimization and that is just not repeatable without an army of engineers, expensive closed source tools, and access to bleeding edge foundries.
What people want, though, isn't to be able to make their own FPGA's. They just want an FPGA that is fully documented. Xilinx and Altera like to keep certain details secret. You have to use their tools because they won't tell you want you need to write your own and, even if you figure it out, they will sue you.
As customization reaches lower and lower levels, it becomes increasingly difficult to meaningfully compromise it. Probably the only way to meaningfully compromise an FPGA is to autodetect an internet connectin, and stream out to it everything you receive, possibly only on receiving a particular activation signal.
The "FP" in "FPGA" stands for "Field Programmable"; it's possible to compromise in the field, in a rather meaningful way.