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fMRI Data Reveals How Many Parallel Processes Run In the Brain

New submitter xgeorgio writes: From MIT Technology Review: "The human brain carries out many tasks at the same time, but how many? Now fMRI data has revealed just how parallel gray matter is. ... Although the analysis is complex, the outcome is simple to state. Georgiou says independent component analysis reveals that about 50 independent processes are at work in human brains performing the complex visuo-motor tasks of indicating the presence of green and red boxes. However, the brain uses fewer processes when carrying out simple tasks, like visual recognition.

That's a fascinating result that has important implications for the way computer scientists should design chips intended to mimic human performance. It implies that parallelism in the brain does not occur on the level of individual neurons but on a much higher structural and functional level, and that there are about 50 of these. 'This means that, in theory, an artificial equivalent of a brain-like cognitive structure may not require a massively parallel architecture at the level of single neurons, but rather a properly designed set of limited processes that run in parallel on a much lower scale,' he concludes." Here's a link to the full paper: "Estimating the intrinsic dimension in fMRI space via dataset fractal analysis – Counting the `cpu cores' of the human brain."

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  1. Re:analog computer by Anonymous Coward · · Score: 3, Interesting

    I think that the distinction you are trying to draw is not digital versus analogue. It is synchronous versus asynchronous circuit design.

    You can build asynchronous digital logic circuits using various self-timing mechanisms. You do not have to use clocked input buffers to synchronize tiers of logic gates, that is just a convention that makes reasoning about the system a lot easier. The design process is much more difficult, as you have to consider many more combinations of signal paths much as in typical analogue circuit design. You can still use thresholds at the gate level to implement digital logic functions, and you can form and react to pulse trains to do things like serial communication of bits without a clock signal. Things like the 8b10b encoding can ensure that the signal remains in a disciplined mode such that timing can be recovered.

    You can envision hybrid designs where more and more self-timed communication happens between ever shrinking domains of conventional synchronous logic. Eventually, the clocking in those domains might be entirely derived from the self-timed input links, and at that point you have what sounds to me like an asynchronous digital system.