Slashdot Mirror
Samsung Announces Production of 20nm Mobile LPDDR4, Faster Than Desktop DDR4
MojoKid writes Samsung announced today that it has begun volume production of its 8Gb LPDDR4 memory chips, with expected commercial shipments in 2015. The announcement is noteworthy for a number of reasons. First, one of the most important characteristics of a modern mobile device is its battery life, and moving to a new memory standard should significantly reduce the memory subsystem's power consumption. Second, however, there's the clock speed. Samsung is claiming that its LPDDR4 will hit 3.2GHz, and while bus widths on mobile parts are significantly smaller than the 64-bit channels that desktops use, the higher clock speed per chip will help close that gap. In fact, multiple vendors have predicted that LPDDR4 clock speeds will actually outpace standard DDR4, with a higher amount of total bandwidth potentially delivered to tablets and smartphones than conventional PCs will see. In addition, the power savings are expected to be substantial.
LP = low power
Power = work / time
and while bus widths on mobile parts are significantly smaller than the 64-bit channels that desktops use
Many chips such as Snapdragon 805 and Apple A8x use dual-channel 64-bit LPDDR3 with about 25GB/s total memory bandwidth.
I'm not sure why they're speculating on the whole "faster than desktop!". What's the agenda here? Higher clocks isn't actually a desired feature, it's what you have to do if the bus is too narrow and you're too cheap do make it wider. If they could afford it, they'd definitely pick a wider bus before higher clocks (and therefore more energy consumption).
Also, desktop DDR4 has been run at 4GHz already.
In short; good luck with that.
the very nature of DRAM is the opposite of low power. Samsung is trying to cut back on the refresh rate by monitoring the temperature. I have a feeling they will fall far short of lab predicted savings considering most phones are stuffed into insulated pockets & purses while they fire off the radio.
It's a shame SRAM was left to rot and so much effort research & infrastructure has been poured into DRAM.
And how are going to "actually outpace standard DDR4", whose song "Drop Out" is already 260 BPM, while keeping it danceable? (Oh wait, that's how.)
" In fact, multiple vendors have predicted that LPDDR4 clock speeds will actually outpace standard DDR4, with a higher amount of total bandwidth potentially delivered to tablets and smartphones than conventional PCs will see."
I doubt it since you could just adapt the LPDDR4 memory for use in a desktop if you have half a brain. Furthermore, since since sub-watt level powersavings aren't really critical on a desktop, if these chips are actually that good then they can be opened up to run faster at a higher power envelope that's still reasonable for a desktop.
AntiFA: An abbreviation for Anti First Amendment.
So does that mean we can expect newer mainstream ATX MBs to use SODIMMs now?
Life is not for the lazy.
So desktops will start to use this too then right?
I'm not sure why they're speculating on the whole "faster than desktop!". What's the agenda here? Higher clocks isn't actually a desired feature, it's what you have to do if the bus is too narrow and you're too cheap do make it wider. If they could afford it, they'd definitely pick a wider bus before higher clocks (and therefore more energy consumption).
LPDDR4 uses VSSq termination, a fancy name for a Resistor of app. 40 Ohm /system trace impedance) to ground. For a high level, the driver sources app. 15mA from Vddq = 1.2V.
With this scheme, a power of 20mW is used for each "1"-Bit transferred - while it lasts.
The total power dissipation for signaling then is
bits_transferred * ratio_of_1_bits * bit_time.
Using twice the number of bit lines and halving the bit rate would double the bit time for each bit, and thus double the power consumed for any given data volume.
Signal propagation on traces in multilayer boards is around 15cm/ns (6 inches). Therefore, at 3Gb/s signaling rate, each bit will occupy just 5cm of the signal trace. For longer traces, there will be several bits on the trace. In this case, power consumption does not increase on first order if you increase the bit rate, as changes in signaling do not charge or discharge a lumped capacitance on the entire line, but just on a part of the line. If you can build a fast enough receiver with a small input capacitance, you can keep the signaling power constant while increasing the bit rate.
A secondary effect of high bit rates is that you need fewer traces, which keeps them short and less densely packed. Less dense packing allows slightly higher trace impedance and less crosstalk, which helps reduce the current for a desired signal swing, and the lower crosstalk allows some less signal swing to begin with.