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Learn Gate-Array Programming In Python and Software-Defined Radio
Bruce Perens writes Chris Testa KB2BMH taught a class on gate-array programming the SmartFusion chip, a Linux system and programmable gate-array on a single chip, using MyHDL, the Python Hardware Design Language to implement a software-defined radio transceiver. Watch all 4 sessions: 1, 2, 3, 4. And get the slides and code. Chris's Whitebox hardware design implementing an FCC-legal 50-1000 MHz software-defined transceiver in Open Hardware and Open Source, will be available in a few months. Here's an Overview of Whitebox and HT of the Future.
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HackRF is designed to be test equipment rather than a legal radio transceiver. It doesn't meet the FCC specifications for spectral purity, especially when amplified. You could probably make filters to help it produce a legal output.
Whitebox is meant to meet FCC specifications for spurious signals that are required when amplification of 25 watts or higher is used. Amplifiers also contribute spurious signals and will usually incorporate their own filters.
HackRF is something that sticks on your laptop via USB. Whitebox is meant to be a stand-alone system or one that is controlled from your Smartphone via a WiFi or Bluetooth link.
Whitebox is optimized for battery power. Using a FLASH-based gate-array rather than the conventional SRAM one makes a big difference.
Bruce Perens.
Chris can explain this much better than I, but we are definitely conscious of the gate-array resource use. Currently we are running within the space of the least expensive SmartFusion II chip, which I think you can get for $18 in quantity. Smartfusion 1 was more of a problem as it didn't have any multiplier macrocells and we had to make those out of gates. SmartFusion II provides 11 multipliers in the lowest end chip, and thus the fixed-point multiply performance of a modern desktop chip for a lot less power.
We are also aware of algorithmic costs. For example we were using Weaver's third method and will probably go to something else, maybe a version of Hartley.
Bruce Perens.
Who needs FPGA when you can go open source ASIC and produce an initial production run for under $50k
Something about the FP in FPGA.
Making a chip is either a huge gamble, or a huge amount of verification, usually both. I can buy an FPGA board for $30, I can reprogram it hundreds of times a day to test some code until it works. Sure formal verification is nice, so is rapid development. I use cheap FPGA boards as logic analysers, oscilloscopes, test generators, VNAs, and rather than trying to build a flash front end gui with a bunch of parameters, I just adjust the verilog or the software in the softcore to implement whatever test set I'm currently working on. Even if I could buy an ASIC in qty 1 for $30, it would still be inferior with a 3 month leadtime. If they could manufacture it overnight and get it to me the next day, it would still be worse than an FPGA.
FPGAs and ASICs are incomparable. I'm working on a project using Altera FPGAs and partial reconfiguration that reprograms a portion of the FPGA at kHz intervals to increase the amount of logic density many fold, basically timesharing for FPGA. That is obviously impossible to do with an ASIC unless that ASIC is an FPGA or contains an FPGA.
The downside to my current approach is each timeshare has to be synthesized and P&R'd separately in Quartus, and aside from editing RAM contents between loads, any logic change requires a half hour P&R run on a host PC. An open source FPGA would mean I could put the synthesis and P&R inside the system and make it self hosting. So would Altera releasing a Quartus build for Arm to run on their own SoCs though the enormous time to P&R would still be a problem.