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Toshiba Announces 3D Flash With 48 Layers
Lucas123 writes: Admitting it has bumped up against a 15 nanometer process wall, Toshiba announced it's focusing its efforts on three dimensional NAND using its Bit Cost Scalable technology (PDF) in order to increase capacity. It has dedicated a Japanese fab plant to it and developed 48-level 3D NAND, which bumps density up 33% over previous 3D NAND flash. The new 3D NAND will be able to store 128Gb of data per chip (16GB). Samsung has been mass producing 32-layer, triple-level cell (TLC) 3D NAND since last October and has incorporated it into some of its least expensive SSDs. Yesterday, Micron and Intel announced their own 32-layer 3D TLC NAND, which they claimed will lead to 10TB SSDs. While Toshiba's 3D NAND is multi-level cell (meaning it stores two bits per transistor versus three), the company does plan on developing a TLC version. Toshiba said it's not abandoning 15nm floating gate flash, but it will focus those efforts on lower capacity applications.
It is excellent tech but they can't stack the cells indefinitely. The approach uses pillars of cells with no cross wiring. All the control circuitry is in one plane at the bottom. This makes it cheap because they only have to mask and etch once: all the way down to the planer circuitry on the bottom. The downside is you can only go so high before the control circuitry can no longer detect the signal from the top layers They could add another layer of control circuitry but the principle cost of making a chip is the masking and etching so it may be just as cheap (and definitely easier) to just make two chips.