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Imagination To Release Open MIPS Design To Academia
DeviceGuru writes: Imagination Technologies has developed a Linux-ready academic version of its 32-bit MIPS architecture MicroAptiv processor design, and is giving it away free to universities for use in computer research and education. As the MIPSfpga name suggests, the production-quality RTL (register transfer level) design abstraction is intended to run on industry standard FPGAs. Although MIPSfpga is available as a fully visible RTL design, MIPSfpga is not fully open source, according to the announcement from Robert Owen, Manager of Imagination's University Programme. Academic users can use and modify MIPSfpga as they wish, but cannot build it into silicon. "If you modify it, you must talk to us first if you wish to patent the changes," writes Owen.
It's very common these days for companies to allow universities to use their technology at the cost of tying the company into the university's patent revenue. And of course this is often publicly-funded research, so not only is the taxpayer paying for the development of patents used to sue that same taxpayer, the patents go directly to a company from academia.
The net effect is to feed intellectual property centered companies at the expense of the technology sector in general and small technology companies in particular.
Bruce Perens.
See OpenRISC, which IMO provides a better path for academia.
Bruce Perens.
Isn't the whole point of an FPGA being able to "burn" a design into a chip rather than "building" it? Are they saying you can only run your modifications through a simulator instead of burning an FPGA to test it?
If so, what's the point of the exercise? Wouldn't it make more sense to have students play with an open sourced or freeware design that they can actually implement and test?
I do not fail; I succeed at finding out what does not work.
Well, it's "talk to us first" which probably means "if you want to patent this, you're going to have to license it to us" sort of deal.
I mean, think about it - the company is offering researchers the chance to work on a live product. If the researchers generate something good, then patent it, the company could find that it is hamstrung because the university it gave research materials to has now blocked it from producing the next-generation product.
Basically the companies want to give researchers materials they need to do their research, but they're also not wanting to shoot themselves in the foot for their generosity (which often includes engineering support at the highest levels) by now being forced to pay huge sums of money for the privilege of furthering research.
So there are several reasons.
One is simple fairness - materials were provided for your research and it would be appreciated to not bite the hands that feed you. So if something gets patented, then perhaps a license to use those patents can be negotiated, with a slight discount
If it results in patents that others are licensing, then maybe a tiny royalty for providing the materials to fund the research.
If a university objects, the simple answer is to not accept the offer and to use other materials.
It's really no different than if a company provided funds for a research grant, except instead of providing cash, they're providing materials.
This is fake openness of the microsoftian sort.
The line about patenting, of course is completely bizarre, as it's unrelated to the previous line about building.
I'm not sure if Own is trying to intentionally confuse the issue, or if he himself has completely lost the plot.
It's only "free" for academia. Virtually every single "soft" technology product anywhere should be 100% free for education and academic use. If you don't understand why, I hope you don't work in marketing.
This is really about a slow company getting this. It's not open-source, it's just good marketing.
On another note, for any company which doesn't give away soft products free for academic/educational use should fire their entire marketing team.
The patent terms are whatever they want them to be. In general "reasonable" and "patent" don't happen together much. And "tiny", well I really doubt it.
Having a company provide funds for a research grant and then reap the patent royalties isn't in general a good thing for society. The student researchers get paid like slave labor (if they get paid at all) and put what may be the best idea of their lives in some company's pockets.
Bruce Perens.
I think you are painting an incomplete picture of what we have done here. Absolutely every university we've talked to has embraced this agreement with open arms. This package is mainly designed for students who are learning about computer architecture at the undergraduate/graduate level and who need lab support material for the course. Giving them access to the open RTL which they can study during their labs is in no way enslaving them to anything - they will be getting a chance to see how a CPU architecture used in millions of devices is being implemented using Verilog.
Some (usually smaller) programmable logic devices are burn-once, including the classic small PLDs. Some devices (including newer versions of classic PLDs) are reprogrammable and nonvolatile like flash memory. Most FPGAs, including the large and very large FPGAs, are volatile, and have to be reprogrammed at each power-up.
OK. Can we see your agreements, please? Because that did sound very much like trolling for additional intellectual property to add to your portfolio.
People who read this article have pointed out three open CPU designs in addition to the one that I remembered.
While your product might be "production ready", please keep in mind that open projects are very often written to a higher standard than commercial ones, and the researchers involved are no less professional than your own developers. And their projects come with fewer intellectual property issues than yours.
Bruce Perens.
I don't think that your statement of a generality applies to the specific, Bruce. The modifier "if you want to patent the changes" must not be discounted. So if you write a research paper on how you can tweak their architecture to produce some feature, you can simply elect not to patent it. If somebody else tries to patent the same thing, even the company in question, your research is prior art that anybody can use to strike the patent down.
As an academic who has done patentable research, I can tell you that universities are keenly interested in building their IP portfolios. And any informed patent holder knows that any violation must be prosecuted, or the validity of the patent evaporates. End result: taxpayers getting sued for violating patents generated 100% within universities with public funding. No company need get involved.
I don't know what century you live in... but universities operate like large corporations these days. They mistreat and underpay their workers as much as the law allows, they build massive IP portfolios, they pay their executives millions of dollars... I could go on.
I cannot see how you can be more dishonest, greedy and evil as a researcher. If anything in IP deserves to be called "stealing" then this is it.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
There is an alternative if one wants to avoid the strings Imagination has attached to the MIPS HDL sources. It's called OpenRISC, and it's from OpenCORES. It's based on the MIPS architecture, but has work-arounds around patented MIPS sections. Go w/ that if you want a fab to fab it out
Berkeley University is pushing really hard to get universities to adopt RISC-V (an Open ISA and set of cores) as a basis for future processor and architecture research. The motivation behind RISC-V was to have a stable ISA that isn't patent encumbered, isn't owned by one company, and is easily extensible (OpenRISC didn't fit the bill here).
I can see that ARM and MIPS would have a problem with this, especially as there is nothing particularly innovative or performance gaining about either ISA, and some recent RISC-V cores have demonstrated similar performance to some recent ARM cores in half the area. This is there way of fighting back against something open that stands to lose them significant marketshare.
This is great news. When I was in college the microprocessor design class used a variant of MIPS though this started the quarter after I took the class. In my class we had to wire-wrap a 16-bit MIPS-like CPU using discrete chips and a couple programmable ones. MIPS is relatively easy to implement for educational purposes due to the simple instruction encoding and clean architecture. MIPS, unlike some other processors like ARM, also allows you to add your own instructions using coprocessor 2 which can be a great way to differentiate a processor and enhance it for different tasks. MIPS is a much simpler design compared to ARM or even PowerPC. MIPS is still widely used, especially in networking devices.
For example, my current employer has added a lot of instructions useful for encryption and hashing as well as some useful atomic instructions.
The move from 32-bits to 64-bits is actually quite clean on MIPS which did not require any major changes to the instruction set other than adding 64-bit instructions and sign-extending the 32-bit instructions. There are a few warts on it, such as the fact that the instruction following a branch instruction is always executed (SPARC is the same way). This is no longer all that useful with modern superscalar architectures and the branch delay slot can't always be filled with something useful. Things are also a bit cramped for 32-bits since only the lower 2GB of memory is available for user-space. Kernel space (KSEG0) is from 0x80000000-0x9fffffff and an uncached copy is at 0xa0000000-0xbfffffff. 0xC0000000 - 0xDFFFFFFF can be mapped using the translation look-aside buffer, making another 512MB available to the kernel. Both of these address ranges map directly to the lower 512MB of RAM which somewhat limits things. In 64-bit mode this isn't a problem though since all addresses are sign-extended. Another nice feature in kernel mode is that all physical addresses can be directly accessed, without requiring any special mapping other than setting bit 63 to 1.
Most MIPS processors do not use a hardware page table walker, instead relying on a software configured translation look-aside buffer. When there's a page miss, a quick interrupt occurs to replace an entry in that table with some hardware assist. This goes back to the original philosophy of keeping the hardware design simple. Due to the way it works, it allows total freedom with how page tables are represented in the operating system though there can be a slightly bigger overhead compared to hardware page tables.
The instruction set is quite clean and the instruction encodings are quite simple with only a few classes of instructions, unlike ARM64. Instruction decoding can be handled with only a few look-up tables. MIPS assembly language is far simpler and straight forward than, say X86 and it's quite mature, though not all processors implement all instructions. Many embedded MIPS processors lack floating point and the multimedia extensions, and many are 32-bit only. This helps cut cost and power when making chips for devices that don't need these features. MIPS also can scale up nicely. For example, the chips I work with currently scale up to 48 cores per chip and with two chips running in tandem Linux runs on 96 cores, all with a coherent cache. The newer ABIs are nice in that the only real difference between N32 and N64 is that pointers are 64-bits instead of 32-bits, just about everything else is the same so you get all of the features of 64-bit registers but keep the compactness of 32-bit pointers. This has been present for many years and is a fairly recent addition to X86 and ARM.
This post is encrypted twice with ROT-13. Documenting or attempting to crack this encryption is illegal.
You've made my point for me.
No, that's just the ignorance of the uninformed that "everybody knows", but it's wrong. You don't lose your patent from failing to enforce it. You might be confusing it with trademarks, which can go into the public domain if you allow them to become generic terms rather than specific brands. And you can sometimes lose the capability of being able to enforce against a specific infringer if you hold back until the market develops, that's the Doctrine of Laches. But you don't lose your patent. Nor would you lose your copyright due to failure to enforce.
Bruce Perens.
Please understand that this is in no way trolling or any for of patent gathering/expansion. The reality behind this program was that teachers needed more resources for their coursework. We reached out to a few universities and everyone was very excited about using real RTL in their courses; for example, most computer architecture courses presenting RISC CPUs have a section on the load/store unit - once presenting the theory, being able to then point to the Verilog code and say "and here is how this is implemented in a MIPS32 CPU" is extremely valuable for students. Then students will go in the lab and use FPGAs to boot Linux and write C or assembly code. This is what will happen in the classroom. Theoretical "what ifs" don't really apply here since we are absolutely working with universities to support them - and not against them. That was never our intention and never will be. Coming back to your point, we expect universities to respect our agreement when they sign up to the program (which essentially says they can't go into silicon production and can't patent changes to our code unless they talk to us first). If they find this agreement too restrictive, we will try to adapt the terms but so far absolutely everyone has been very supportive and positive about this.
Microsoft has an "Open License" which allows you to look at Windows NT source code. it's "open", yes? pay them $USD 1m per year, you get an "open" look at the source code of Windows NT. but if you ever dare to use it, talk about it, or do ANYTHING other than *read* it.... they will sue the fuck out of you.
bottom line: can we PLEASE stop using the word "open" in context with these types of stupid, stupid proprietary arrangements? it really isn't helping.
there are plenty of *LIBRE* licensed implementations of MIPS out there: many people have pointed that out (in comments i can see above this one), they're on http://opencores.org/ - there are at least eight MIPS core implementations that i can see, there, possibly the best one (most complete) is this: http://opencores.org/project,m... which has a 5-stage pipeline and a harvard architecture.
so please, stop using the word "open" to refer to proprietary, restricted and patented material.
I think this agreement is better than what my university has now. We also did some work at university with a production level design, but it required signing several very serious NDAs just to follow the course.
I heard they were looking into using OpenRISC but the architecture does not fully match the course so it would be a lot of work. This kind of deal would look useful to me, since bachelor students are very unlikely to create patentable stuff for a simple class project of 20 hours (well ok, with the current standars for patenting something they can probably produce several key innovations in this timeframe).
You've made my point for me.
No, that's just the ignorance of the uninformed that "everybody knows", but it's wrong. You don't lose your patent from failing to enforce it. You might be confusing it with trademarks, which can go into the public domain if you allow them to become generic terms rather than specific brands. And you can sometimes lose the capability of being able to enforce against a specific infringer if you hold back until the market develops, that's the Doctrine of Laches. But you don't lose your patent. Nor would you lose your copyright due to failure to enforce.
True you won't lose the patent, but there is a time limit on suing an infringer, isn't there?
Anyway, given that textbooks often discuss MIPS, good to see something being offered to Academia.
It is a time-limit on damages, which is not the same thing as a time limit on lawsuits. There is still the potential to restrain an infringer who started 6 or more years ago from further infringement through the courts - and totally kill their business - even though damages for the infringement can not be recovered. And you can sue any other infringer.
Bruce Perens.
I found the commenter who posed this as a response to RISC-V interesting. The University of California at Berkeley has a completely public implementation, under the BSD license, without patents filed, which your effort appears to be positioned against.
Bruce Perens.
There is a number of advantages of MIPSfpga over RISC-V including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)
There is a number of advantages of MIPSfpga over RISC-V and OpenRISC including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have interest in teaching their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)
FPGA is reconfigurable hardware.
Verilog code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC.
MIPSfpga has a clear path to commercialization. The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
The problem with open-source MIPS clones - they are not tried in the industry much.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
You can put your design in silicon - with a commercial license.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.