Well, this core is useful for a number of student project. For example, the students can implement a multicore system on chip that consist of a lot of non-coherent cores for specialized computations. Or, for example, they can substitute L1 cache with their own cache that implements MESI protocol or some multicore coherency protocol they invent. Even for the basic course they can connect wires to the internal registers and observe basic pipeline execution.
Sure, you can do the same thing with educational subsets of MIPS (there are many of them). But they frequently lack some important features (like properly implemented exception processing, or TLB MMU etc).
On the other hand, you don't want to teach the intermediate students with a complicated out-of-order superscalar processor with hardware support for multithreading, hardware-assisted virtualization, vector extensions and other features. You will just confuse the students. Complicated processors is another step.
You can put your design in silicon - with a commercial license.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
The problem with open-source MIPS clones - they are not tried in the industry much.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
Verilog code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC.
MIPSfpga has a clear path to commercialization. The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
There is a number of advantages of MIPSfpga over RISC-V and OpenRISC including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have interest in teaching their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)
There is a number of advantages of MIPSfpga over RISC-V including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)
Slashdot Mirror
*** Really? Usually we want to use something for teaching that's easy to understand and modif ***
I agree, what I actually meant is:
1. To illustrate the basics of pipelining, stalls and forwarding it is better to deal with a very simple subset processor
2. However eventually it is useful to show the students a real industrial core as well
So in my opinion it is better to use both: simple subsets and industrial cores
Well, this core is useful for a number of student project. For example, the students can implement a multicore system on chip that consist of a lot of non-coherent cores for specialized computations. Or, for example, they can substitute L1 cache with their own cache that implements MESI protocol or some multicore coherency protocol they invent. Even for the basic course they can connect wires to the internal registers and observe basic pipeline execution.
Sure, you can do the same thing with educational subsets of MIPS (there are many of them). But they frequently lack some important features (like properly implemented exception processing, or TLB MMU etc).
On the other hand, you don't want to teach the intermediate students with a complicated out-of-order superscalar processor with hardware support for multithreading, hardware-assisted virtualization, vector extensions and other features. You will just confuse the students. Complicated processors is another step.
You can put your design in silicon - with a commercial license.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
The problem with open-source MIPS clones - they are not tried in the industry much.
MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
FPGA is reconfigurable hardware.
Verilog code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC.
MIPSfpga has a clear path to commercialization. The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
There is a number of advantages of MIPSfpga over RISC-V and OpenRISC including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have interest in teaching their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)
There is a number of advantages of MIPSfpga over RISC-V including:
1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not some subset or a core created in academia and not tried in industry much.
3. MIPS architecture has large ecosystem (a dozen of commercial RTOS-es, Linux, compilers, etc)
The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.
(The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC)