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New Network Design Exploits Cheap, Power-Efficient Flash Memory
jan_jes writes: The researchers at MIT were able to make a network of flash-based servers competitive with a network of RAM-based servers by moving a little computational power off of the servers and onto the chips that control the flash drives. Each server connected to a FPGA and each FPGA, in turn, was connected to flash chips and to the two FPGAs nearest it in the server rack. As it is connected to each other, they created a very fast network that allowed any server to retrieve data from any flash drive. Finally, the FPGAs executed the algorithms that preprocessed the data stored on the flash drives.
You should do a search on fpga. You clearly dont know what it is.
Huh? Field Programmable Gate Arrays allow for redefinable digital logic whose function is limited by the internal signal propagation delays. This allows digital functions to performed very quickly. Compare this to a program that has to process a bunch of instructions to perform logical operations - very flexible but very slow in comparison. I don't understand why you equate digital logic to non-volatile memory arrays.
Greed is the root of all evil.
Through in 4 gigs of ram, too!
The law is a weapon of the government, not a protection for the likes of you. Surely you understand that.
Go back and look at an AS/400, iSeries, i5 and now called IBM i,
Biggest machine I worked on, 32 cores and 3/4TB of ram. And that was still ovly 1/2 as big it could be. But that 3/4TB was not the total ram in the machine, it had IOPs and IOAs that oversaw the the disk drives. Those processors had large ram and were basically fast and faster cache. So our machine with 900 drives in multiple raid-6 groupings (IOPs) with multi-grouping in IOA, acted as a 900 drive raid-0 (stripe) to main core. So reading a file sequencially all the drives will start suppling data first data in 50ms... but then the rest was "just there". Processing 4 billion row history files was easy.
Well, I actually wonder if this isn't something new.
So, think about it, because (I think) this kind of extends a Von Neumann architecture.
It gives you a larger degree of parallelism because all the little doohickies are using their local storage to do some of your tasks.
To me it sounds like they've created something which helps with parallelism on huge data sets.
My guess is your cheap quad core isn't as cheap or suited to these tasks as you think.
Lost at C:>. Found at C.
The EMC Isilon is a cluster of FreeBSD nodes with completely customized filesystem on top. All the nodes are connected to each other by Infiniband, and redundancy is built into OneFS.
I'm visualizing this as someone adding FPGA cards to Isilon nodes, and installing SSDs instead of the usual HDDs in the array. Innovative, but this isn't revolutionary by any means.
I don't understand why you equate digital logic to non-volatile memory arrays.
You're simply underestimating the propensity of some people to proudly display their ignorance to the world.
Irony: Agile development has too much intertia to be abandoned now.
Well FPGAs often do throw in an ARM core or 4 these days:
https://en.wikipedia.org/wiki/Field-programmable_gate_array
e.g. the A Xilinx Zynq-7000 includes a Dual Core Cortex A9 on the chip.
Logic gates are fine, but sometimes you just need some serial execution of code!
This comment reminded me a little of this Wondermark comic.
You are not alone. This is not normal. None of this is normal.
Lol, that's beautiful. If I had mod points, they'd be yours.
Just cruising through this digital world at 33 1/3 rpm...
Because general purpose processors are slower than a specific purpose module in an FPGA could be. Cheap is not an important consideration in this case.
Wow ... No solid states? Sucks to be you, bro!
I art more snarky, and terse than thou. I art Slashdot!
The article explains how it's cost effective and they uses FGPAs contributed by their sponsors.
If they had sponsors to give them free RAM somehow I imagine that would have tipped the price comparison the other direction.
http://lkml.org/lkml/2005/8/20/95
Only on an abstraction level so high that it is not useful anymore. Sure, FPGA these days is flash-backed these days (used to be EEPROM backed) with the logic-cells actually being RAM-backed and loaded on power-up from FLASH, but storing data and storing logic-configuration is a bit different in most circumstances.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
Simple: That would not produce papers, PhDs and press-statements.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
FPGA is just gimmicked flash sandbagged with a liberal topping of patents. The fundamental patents are getting long in the tooth, keep an eye on those expiry dates. See the obvious connection with OP.
You could make a great character in a Dilbert comic.
You're simply underestimating the propensity of some people to proudly display their ignorance to the world.
Indeed. Go here. Then read: Conguration Cell Technology: FLASH
When all you have is a hammer, every problem starts to look like a thumb.
Ah, somebody who actually has a clue. (But drew the wrong conclusion anyway.)
When all you have is a hammer, every problem starts to look like a thumb.
Heh, that's amusing considering the zero content nature of your reply, coupled with supreme confidence in the pure, unadulterated wit of it. I guess there's a dilbert comic in there somewhere, but not starring me.
When all you have is a hammer, every problem starts to look like a thumb.
OK, explain to us how FPGA and Flash ROM are the same thing.
"Wrong conclusion" as in "does not agree with you"? Not very mature.
And no, the actual logics functionality of FPGAs is _not_ rendered by FLASH cells or even the more modern RAM cells. They just provide the interconnect matrix and the logic-cell internal connections, _not_ the logic.
Methinks the clue is very absent from your view of things.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
I think this person may look-up table implemented logic (where the configuration is in the bits stored in the table) and gate-array implemented logic (where the configuration is in the connections between the gates and the config bits statically drive "switches" sitting in the connections).
Seems also to be a classic case of "incompetent and unaware of it" as the mere name Field Programmable Gate Array rather strongly says it is not the look-up table based thing, but the gate array thing.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
I should have also predicted that you'd double-down on that statement rather than attempting to educate yourself. Did you just see that flash memory was mentioned in an FPGA-related document without actually understanding the context? Because it sure looks like it to me.
Here, I've got a PDF of my own to show you. This one explains quite clearly that there are multiple ways to store configuration data for an FPGA, and that flash-based memory is only one of several options. I'll summarize in the hopes that you or someone else will learn something even without reading the link.
FPGAs are essentially a set of configurable logic circuits, and this obviously requires a set of configuration data to operate as designed. The higher-level nature of the logic circuits makes FPGAs more efficient than a general-purpose CPU for some specialized types of tasks. There are several ways to apply that configuration data on a device:
* Some FPGAs use flash memory or a master computer as a permanent external store, but use SRAM to maintain the internal configuration state. These devices need to be configured after power-up by the external storage (whether flash or something else), and the SRAM needs to be powered to maintain state.
* Some devices use flash memory internally to maintain the configuration state, rather than as a two-step process.
* Some devices uses anti-fuse circuits to maintain configuration state. These devices, once programmed, can't be altered. No flash or other memory is needed for these types, as the circuitry is essentially physically altered in place with the initial programming.
So, in two out of three commonly-used cases, flash memory isn't even used in the FPGA itself. This isn't even counting the early models that could reset their EPROM-based configuration with an ultraviolet light through a quartz window on the chip itself.
Seriously, just admit when you're wrong.
Irony: Agile development has too much intertia to be abandoned now.
You're simply underestimating the propensity of some people to proudly display their ignorance to the world.
Indeed. Go here. Then read: Conguration Cell Technology: FLASH
The Flash chip is typically just a helper chip outside the FPGA. The logic configuration is transferred from the Flash to the FPGA every time when the system is started. But the general concept of FPGA is not about Flash. The general concept of FPGA is about a type of digital logic which can be changed easily.
Well, maybe we roasted you a bit too much. :) Sorry about that.
The one thing that comes to mind is, "Could I replicate the findings?" What would I need?
Moving some processing out of the central processor and into processors that access storage is not exactly new.
But I bet these servers don't look too terribly much like CDC 6000s. (Especially their FPGA parts.)
The article should be an interesting read. Which I will get to soon, now that I've offered an uninformed opinion about TFA and incidentally exposed my geezerhood.
There's no time like the present. Well, the past used to be.
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Something along those lines -- in a very different era -- were the CDC 6000 series computers designed by Seymour Cray, and their successors.
One or more central processors did the number crunching and general program logic, and some of the OS, with a bunch of smaller, not-so-bright "peripheral processors" doing I/O and certain low-level OS functions. (How not-bright? They couldn't do division or multiplication except by powers of two, for instance.)
Supposedly, Gene Amdahl, designer of the IBM 360 series machines, later said he wished he'd put more smarts into the channel controllers, in the manner of the CDC machines. Don't have a source. That story might be apocryphal, or at least misremembered in its details.
There's no time like the present. Well, the past used to be.
A bottom of the range FPGA - 200 I/O pins, with 216.5 Gb/s for $20.
And the one I have sitting on my desk at the moment has about 500 Gb/s over about 300 pins..
You can't get that on an ARM CPU.