Intel Broadwell-E, Apollo Lake, and Kaby Lake Details Emerge In Leaked Roadmap

bigwophh writes: In Q4 2016, Intel will release a follow up to its Skylake processors named Kaby Lake, which will mark yet another 14nm release that's a bit odd, for a couple of reasons. The big one is the fact that this chip may not have appeared had Intel's schedule kept on track. Originally, Cannonlake was set to succeed Skylake, but Cannonlake will instead launch in 2017. That makes Kaby Lake neither a tick nor tock in Intel's release cadence. When released, Kaby Lake will add native USB 3.1 and HDCP 2.2 support. It's uncertain whether these chips will fit into current Z170-based motherboards, but considering the fact that there's also a brand-new chipset on the way, we're not too confident of it. However, the so-called Intel 200 series chipsets will be backwards-compatible with Skylake. It also appears that Intel will be releasing Apollo Lake as early as the late spring, which will replace Braswell, the lowest-powered chips Intel's lineup destined for smartphones.

Comments

native USB 3.1 is not that big of a thing

[Joe_Dragon]

native USB 3.1 is not that big of a thing as on most board be it native or add on chip it's still over the same DMI bus.

Now intel needs to add more cpi-e to the cpu. At least 20 lanes + DMI. 16 for video and 4 for other stuff like TB 3.0 PCI-e SSD's.

Re:native USB 3.1 is not that big of a thing

[viperidaenz]

Since USB 3.1 Gen 2 is faster than a PCI Express 3.0 lane, perhaps it's better to implement it closer to the CPU and memory controller?

Re:native USB 3.1 is not that big of a thing

[blankinthefill]

One of the issues that I've been running into for a long while, and expect to be running into even more with the expansion of the M.2 and related slots, has been the serious lack of PCI-E lanes that Intel supports. It's very easy, running SLI and one of two other things that use PCI-E, to run out of PCI-E lanes on today's boards, especially if you're a power user. And with new expansion slots for SSDs and other applications starting to enter the market, using multiple PCI-E lanes (up to 4 for a single M.2 slot), it's going to be even easier to suck all those lanes up and still need more. Honestly, for some power users, Intel could probably double the number of PCI-E lanes natively supported, and still not provide enough.

Re:native USB 3.1 is not that big of a thing

[viperidaenz]

There's quite a few PCI-E lanes.

16 directly from the CPU
20 from the chipset via the DMI link (in the Z170, it was 8 2.0 lanes prior). The new chipset for these new CPU's ups that to 24 lanes.
That's a total of 40 PCI-E 3.0 lanes.

Re:native USB 3.1 is not that big of a thing

[sexconker]

2 video cards will take 32 of them, a high end SSD will take up 4, if you've got a wireless card, a sound card, or some other shit you're eating a couple more. And then you've got all the legacy SATA ports and whatnot that may eat up some of those lanes opportunistically.

40 is by no means future-proof. I'd like to see 48 or 64 for a pro/enthusiast rig,

Re:native USB 3.1 is not that big of a thing

[Joe_Dragon]

The DMI link from the CPU is only pci-e X4

Upcoming names

[Anonymous Coward]

when does Intel "Cornf Lake" come along?

We're almost at the end with current tech

[tkrotchko]

14nm for these chips puts us close to the end of currently deployed technologies for transistor densities.

"The path beyond 14nm is treacherous, and by no means a sure thing, but with roadmaps from Intel and Applied Materials both hinting that 5nm is being research, we remain hopeful. Perhaps the better question to ask, though, is whether itâ(TM)s worth scaling to such tiny geometries. With each step down, the process becomes ever more complex, and thus more expensive and more likely to be plagued by low yields. There may be better gains to be had from moving sideways, to materials and architectures that can operate at faster frequencies and with more parallelism, rather than brute-forcing the continuation of Mooreâ(TM)s law."

http://www.extremetech.com/com...

Re:We're almost at the end with current tech

[JoeMerchant]

We've been moving sideways for 10 years. In the 20 years before that, clock speeds were doubling every year or two. For the last 10, we've moved from a norm of single cores to a norm of 4 (or 2 + "Hyperthreads"), rotating hard drives to SSD, and specialized architectures to support HD video, but clock speed has been basically stagnant while the processors are getting fatter, more parallel, and not just in core count.

10 years ago, Intel was hinting at a massively parallel future (80 core processor rumored in development at the time), they've been slow to deliver on that in terms of core count, but are making progress on other fronts - especially helping single cores perform faster without a faster clock.

Re:We're almost at the end with current tech

[Gadget_Guy]

That's like walking over an unfinished bridge.

No problem. If you close your eyes the quantum bridge will be both finished and unfinished.

Re:We're almost at the end with current tech

[Kjella]

The real problem is that we're mostly redistributing the watts.

4 core @ 4GHz (i7-4790K) = 91W, 4*4/91 = 0.175 GHz/W
4 core @ 3.2GHz (i7-4790S) = 65W, 4*3.2/65 = 0.197 GHz/W
4 core @ 2.2GHz (i7-4790T) = 35W, 4.*2.2/35 = 0.251 GHz/W

So from top to bottom we're seeing 40% better perf/W with perfect linear scaling. Neat, buit not exactly revolutionary when you subtract overhead. We've already got so much scale out capability that power is clearly the limiting factor:

8 core @ 4GHz (doesn't exist) = ~185W
8 core @ 3.2GHz (1680v3) = 140W
8 core @ 2.2GHz (2618Lv3) = 75W
16 core @ 4GHz (doesn't exist) = ~370W
16 core @ 3.2GHz (doesn't exist) = ~280W
16 core @ 2.2GHz (E7-8860v3) = 165W

We can't go faster or wider unless we find a way to do it more efficiently, either that or we need extremely beefy PSUs and water cooling.

Re:We're almost at the end with current tech

[gweihir]

Chips basically have components (transistors, diodes, capacitors, resistors, and recently inductors) and interconnect ('wires').

Interconnect has been the primary speed-limiter for about 20 years. At 5GHz or so, it starts to become exceptionally difficult to get signals from one component to the next, and in particular distributing clocks becomes a limiting issue as clocks need long wires in order to reach everything. Making transistors smaller helps a bit because the wires get shorter and signal-strength (voltage) can be reduced. But that effect is limited and seems to have mostly reached its end.

The overall effect is that extreme over-clocking for the 15 year old Pentium 4 could reach 8GHz, but current chips do not do much better with both AMD and Intel going up to about 9...10GHz as absolute maximum.

Re:We're almost at the end with current tech

[nateman1352]

10 years ago, Intel was hinting at a massively parallel future (80 core processor rumored in development at the time)

I think the 80 core processor Intel was developing at the time eventually turned in to the Knights Corner aka Xeon Phi chip. Originally Intel developed this tech for the Larrabee project, which was intended to be a discrete GPU built out of a huge number of X86 cores. The thought was if you threw enough X86 cores at the problem, even software rendering on all those cores would be fast. As projects like llvmpipe and OpenSWR have shown, given a huge number of X86 cores this isn't as crazy of an idea as it initially sounds... but still a little crazy :) Ultimately Intel cancelled that project and decided to use that tech for super computing instead of graphics. A result of this is Intel retained the "Gen" design for their graphics core, which is a more traditional GPU design.

Re:We're almost at the end with current tech

[Alomex]

10 years ago, Intel was hinting at a massively parallel future (80 core processor rumored in development at the time),

An Intel higher up told me a while back that they could ship them today if they wanted. The problem is that users in the field report having a hard time using more than 6 cores outside host virtualization. Since then Intel has been dedicating the extra real estate to more cache, which programs can easily take advantage of, and less to cores, which no one knows quite how to use beyond 6 to 8 cores.

Re:We're almost at the end with current tech

[slew]

Interconnect gets smaller if you reduce speed as well when you reduce size. If you keep speed constant, interconnect stays the same size and it will consume the same amount of power. Well, roughly. The problem is that at these speeds you are dealing with RF laws, not ordinary electric ones and RF laws are pretty bizarre.

The problem can easily be described to first order "electrically". No bizarre RF laws necessary.

Interconnect is dominated by "resistive" issue (a good approximation of RF-impedance) and capactive coupling (a good approximation to RF field effects)... Since the interconnect is relatively getting thinner and longer, the resistance of that wire is going up (R ~ L/w/h) and it capacitively couples more with nearby lines (Cild = W*L/X or Cimd = H*L/Ls) and makes it take longer to move charge to and from the gate.

Second order effects are mostly "noise" and edge-rate coupling, but even then aggressor/victim and crosstalk issues can be thought of mostly as just distributed "lumped" approximation (e.g., capacitance per um, and mutual inductance per um) where the result is coupling being different at higher frequencies and spacing. No bizarre RF need to get the gist (well, no more than the basic concept of a wall-wart transformer)...

Looks Like My i7-920 @3.8 Ghz

[zenlessyank]

Just needs to last 5 more years. Hopefully a real reason to upgrade will happen around 2020.

Re:3+GHz speeds, extra cores, more lanes.

[JoeMerchant]

Do problems really have to scale up to consume the available compute power?

Big CPU suckers like Monte Carlo and HiDef video processing are near trivial to parallelize, while most "normal" compute tasks are sub-millisecond on a single 2GHz thread, especially with FPU and other specialized instructions.

Granted, as camera prices fall, I want to have real-time intelligent video processing on an array of 20 cameras, but, can you spot the parallel opportunity there?

Re:Nor is HDCP 2.2

[mrchaotica]

No. People want to play media. They have no desire whatsoever to have it "protected" against them.

Re:3+GHz speeds, extra cores, more lanes.

[gweihir]

That is unlikely to happen. Parallelizing most things is orders of magnitude more complex than writing them single-task, and for quite a few things it is either impossible or gives poor results.

Re:Nor is HDCP 2.2

[Kjella]

No. People want to play media. They have no desire whatsoever to have it "protected" against them.

People also would rather not pay for their media, so if they have to choose between protected content and no content at all (because the content providers think that it is not economically viable enough for them to release it DRM-free) then the consumer will choose the former option. And if the protection is implemented well so that it doesn't adversely affect the consumer then they probably wouldn't give a damn.

I think you confused "not economically viable" with "profit maximizing". You think that famous artists, movie stars and authors that make tens of millions of dollars would say "Nah, I'd rather go work at McDonald's" if you cut their wage in half? And I'm sure you noticed how the music industry imploded after iTunes gave up the DRM. Oh wait, it didn't. And there's a whole lot of countries I'd live in if North Korea was the other option, we don't have to allow unreasonable terms if we don't want to. Just because it would be economically profitable to weld shut the hood of the car and control how you drive it after you've sold it, doesn't make it right. The doomsday scenarios are false. We could easily drop the DRM-protection, ban DRM and go back to plain old copyright infringement without the world coming to an end.