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Thanks For the Memories: Touring the Awesome Random Access of Old (hackaday.com)
szczys writes: The RAM we use today is truly amazing in all respects: performance, reliability, price; all have been optimized to the point you can consider memory a solved problem. Equally fascinating is the meandering path that we've taken over the last half century to get here. Drums, tubes, mercury delay lines, dekatrons, and core memory. They're still as interesting as the day electrons first ran through their circuits. Perhaps most amazing is the cost and complexity, both of which make you wonder how they ever manage to be used in production machines. But here's the clincher: despite being difficult and costly to manufacture, they were all very reliable.
Alpha Particles from space do not penetrate the building that the computer is in, nor the computer case, nor the plastic package of the memory devices themselves.
Alpha particle bit errors are caused by alpha particle emissions within the memory cell itself, as there is a minute amount of radioactive material in all semiconductor devices, including memory.
However, radiation-induced bit errors are seldom actually caused by package alpha particle emissions. The more likely space-related culprit is neutron flux. It has been found that DRAM bit error rates increase dramatically with altitude, and that solar events increase the rates further.
Fun stuff.
slower than even the slowest CPU cache.
CPU cache IS MEMORY, so how can it be slower than itself?
And before I quote the rest of your trash and make you look stupid, lets point out the most important fact here:
You can have RAM that runs as fast as CPU cache, you just can't afford it.. That CPU with 12MB of CPU cache is mostly expensive BECAUSE OF THE 12MB OF CACHE. and the difficulty in getting that much RAM to operate reliably at those speeds results in low yields, and increased consumer cost.
Even assuming we use the entire ~12MB of L3 cache as instruction cache (which is impossible really unless those instructions don't require any data access, which is utterly implausible), any modern CPU can blow through that in much less time than it takes a DDRx memory controller to set up a RAS.
Did you seriously imply that a Xeon CPU can blow throw 12MB of instruction cache in the amount of time it takes to do one complex instruction? That IS what you said. Which takes what? 40 clock cycles total, in the extreme worst case? (on anything with a 12MB cache which are going to all be high end/fast chips). So you're claiming that in 40 clock cycles it can empty a 12MB cache ... No. In 40 clock cycles ... it can load EXACTLY 40 registers with data from cache ASSUMING IT DOESN'T DO ANYTHING ELSE. So awesome, you just loaded 320 bytes of RAM into CPU registers ... and didn't use it for anything at all.
Do a BSR or BSF on 64 bit number takes 16 clock cycles all by itself!
The one and only thing slower than memory access is disk access, and even there we are closing the gap. Memory has not gotten appreciably faster in a decade, unless of course you ask marketing people.
DDR3's base rate is 800MT/s. DDR4's base rate is 2133MT/s ... yea, 2.5x is not appreciably faster or anything.
The one and only thing slower than memory access is disk access, and even there we are closing the gap.
Awe thats cute, you think SSDs are somewhere near RAM speeds. Just because SSDs are ridiculously fast at some things compared to spinning rust doesn't make them magically fast. We've had disks on arrays capable of saturating CPU bandwidth for years too.
This is literally the stupidest thing I've seen posted on Slashdot in a long time, since at least yesterday!
If you're referring to your post, then yes, I agree. It is pretty fucking stupid.
Do you know what DDR means? It means DOUBLE data rate. Twice as fast. (not really, but close enough for hand grenades). Do you have any idea what DDR2 did on top of that? And 3 ... and 4 ...
Persistent Volume manager for Kubernetes - https://github.com/dwimsey/openshift-pvmanager
Yes and no, if you are thinking about your computer or single server sitting beside you. If you are thinking of next gen data centers and virtualized servers, being able to supply a bus to RAM over a fiber link is very interesting.
Infiniband essentially already does this: it's a high speed, low latency interconnect which provides remote memory access and works over copper or fiber. It's only moderately low latency though, since the speed of light is limited.
Every meter gives 3 nanoseconds of latency, more like 4 because the signals are sub-luminal in speed. You won't have to have a long cable before you add a serious latency penalty compared to local RAM. That's never mind the protocol and networking overhead, which for infiniband (which is designed for low latency for supercomputers) is still 500ns, dwarfing the RAM latency.
There have in fact been systems made to essentuially build virtual machines with distributed memory like this. The trouble is they suck beause the code is written assuming fast access to RAM.
Big supercomputer codes which essentially have to deal with this all the time use MPI, so they can know about the high latency (i.e. 500nS) transfers and schedule them long in advance.
SJW n. One who posts facts.
The bit flips aren't due to neutrons, but to other high energy particles (cosmic rays).
And modern memory design tolerates this quite well (on chip EDAC, for instance).
But that's not the dominant source of errors any more. It's more things like electrical noise (signal integrity is another term). As you reduce the size of the device holding a single bit, you're starting to get down to where the thermal noise is a significant fraction of the "signal" (i.e. the presence or absence of charge in that bit storage).