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Intel Says It Will Move Away From 'Tick-Tock' Development Cycle
An anonymous reader writes: In its latest annual report, Intel says that it will be moving away from its decade-old "tick-tock" strategy (PDF) for developing new chips. From the company's 10-K filing, "We expect to lengthen the amount of time we will utilize our 14nm and our next generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions." Anand Tech's Ian Cutress explains, "Intel's Tick-Tock strategy has been the bedrock of their microprocessor dominance of the last decade. Throughout the tenure, every other year Intel would upgrade their fabrication plants to be able to produce processors with a smaller feature set, improving die area, power consumption, and slight optimizations of the microarchitecture, and in the years between the upgrades would launch a new set of processors based on a wholly new (sometimes paradigm shifting) microarchitecture for large performance upgrades. However, due to the difficulty of implementing a 'tick', the ever decreasing process node size and complexity therein, as reported previously with 14nm and the introduction of Kaby Lake, Intel's latest filing would suggest that 10nm will follow a similar pattern as 14nm by introducing a third stage to the cadence."
New instructions don't change the fundamental flow of data inside the processor. In the PPro presentation, they said that the FPU needed 86 bit wide busses (80 bits data + status) and that this was " a lot of bits". Now they have AVX256 and 512 is right around the corner. Using parallelism to implement vector instructions is great for some tasks, but a compiler, for example or an interpreter (Python, Ruby, Perl) still executes mostly basic i386 instructions (or their 64 bit extensions).
Making the instruction set byzantinely complex does not help programmers and compiler writers, and the encoding is so complex that there two instruction caches on some processors: one in the native, inscrutable encoding, and one in another encoding easier on the decoders and schedulers. A saner, simpler, encoding (ARM and MIPS are quite good in this respect) would avoid this dual cache (which in the end means that the first level instruction cache is smaller because of transistor budgets).
I'm not picking on you in particular, but I'm seeing a lot of posts implying that Moore's law could keep going but it's too expensive, there's not enough competition to warrant it, etc. The fact is that physics is the nail in the coffin for Moore's law. Making small fab processes is getting more and more difficult because these size scales are super tiny, and the difficulty means that Moore's law simply cannot keep going because we have to develop fundamentally new technology -- not just scaled down current technology.
There's a reason Intel is planning to stop using Silicon at 7 nm (not clear what they'll move to -- maybe indium gallium arsenide), and getting up to production quality with a new material is a huge task that is fundamentally incompatible with Moore's law. (InGaAs is not "new" per se, but InGaAs has never seen real commercial use; it has been confined to research labs.)
There's also a reason that research in classical (not only quantum) computing with superconducting circuits is again being seriously researched by commercial enterprises -- including companies like Northrup Grumman which are not traditionally associated with designing computer chips. (IBM poured a lot of money into superconducting computers in the 1980s but ultimately gave up because Si computing was marching along just fine. I think that IBM is back in the superconducting game too.) Again, getting superconducting circuits up and running is _hard_ and fundamentally incompatible with Moore's law.
Moore's law is intrinsically dead. End of story. Even if/when the non-Si chips get up and running, I don't expect that Moore's law will be revived. 7 nm equates to about 14 silicon atoms. The end of the road is in sight. It's trying to march through quicksand from here on out.
PS. I don't get the "lack of competition" hypothesis for why Intel is slowing down; there are a number of manufacturers matching or closing in on Intel's fab process. E.g. Samsung and Globalfoundries are already at 14 nm. TSMC is at 16 nm. These aren't in direct competition with Intel at the moment, but they will be if Intel ever gets serious about putting their chips in things other than desktops/laptops/servers. Intel isn't stupid; they see these other companies as competitors, and Intel really wants a leg up on them. If Intel could keep up with Moore's law, they would.