Samsung Starts Mass Producing Industry's First 10-Nanometer Class DRAM (engadget.com)

An anonymous reader writes: Samsung is now mass producing the industry's first 10-nanometer class, 8Gb DDR4 DRAM chips, ahead of competitors SK Hynix and Micron. It will produce 10nm-class DDR4 DRAM modules this year varying from 4GB for laptops and up to 128GB for enterprise servers. Samsung also promised to reveal 10-nanometer-class mobile DRAM "in the near future." The announcement marks a big milestone for the company after it first mass produced 20-nanometer-class 4GB DDR3 DRAM chips in 2014. "Samsung's 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry," said Young-Hyun Jun, President of Memory Business, Samsung Electronics. "In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users."

Comments

Classy use of Class

[MiniMike]

FTFA:
*10nm-class denotes a process technology node somewhere between 10 and 19 nanometers, while 20nm-class means a process technology node somewhere between 20 and 29 nanometers.

This has the stink of a marketing department on it. Does anyone know what the actual size is? I'm guessing it's closer to 19 nm than to 10 nm. Still an impressive achievement if it meets their claims.

Next year will their marketing department tout their 0 nm-class* process technology?

Re:Classy use of Class

[tlhIngan]

This has the stink of a marketing department on it. Does anyone know what the actual size is? I'm guessing it's closer to 19 nm than to 10 nm. Still an impressive achievement if it meets their claims.

Well, general random logic is at 22nm, and memory class devices are usually a half-node ahead, so 16-18nm would be the size. Size is less important for general logic as most transistors will be larger than minimum size as transistors aren't the limiting factor - wiring is. Most transistors are larger because there's plenty of space as the wiring is keeping the transistor density low. Enough such that designers often put in extra transistors and gates in a design to be able to allow for metal layer redesigns without affecting transistor level placement.

In memory units, minimum transistors are the storage elements, so the smaller they are, the more you can fit in. Plus, their extreme regularity means you want to minimize the cell size as much as possible.

General logic is sparse enough that in what a few hundred thousand transistors occupies for random logic may be occupied by millions for memory blocks.