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Microsoft Details Its 24-Core 'Holographic Processor' Used In HoloLens (pcworld.com)

Posted by BeauHD on from the technical-specifications dept.

The processor powering Microsoft's HoloLens augmented reality headset has been a mystery -- until now. During the annual Hot Chips conference in Cupertino, California, Microsoft revealed some juicy details about the secretive chip. PCWorld reports: "The HoloLens' HPU is a custom 28nm coprocessor designed by TSMC, The Register reports. The chip packs 24 Tensilica digital signal processor (DSP) cores. As opposed to more general-purpose CPU cores, DSPs are a specialized technology designed for rapidly processing data flowing in from the world -- a no doubt invaluable asset while rendering augmented reality environments in real time. Microsoft's HPU also contains roughly 65 million logic gates, 8MB of SDRAM, and 1GB of traditional DDR3 RAM. It draws less than 10W of power, and features PCIe and standard serial interfaces. The HPU's dedicated hardware is up to 200 times faster than performing the same calculations via software on the less-specialized 14nm Intel Cherry Trail CPU. Microsoft added custom instructions to the DSP cores that allow the HPU to churn through HoloLens-specific tasks even faster, The Register reports. The HPU can perform roughly 1 trillion calculations per second, and the data it passes to the CPU requires little additional processing."

4 of 113 comments (clear)

  1. 1 trillion calculations per second by Anonymous Coward · · Score: 5, Funny

    How many of those 1 trillion calculations per second are for telemetry and serving ads?

  2. Give up, Microsoft by Anonymous Coward · · Score: 5, Insightful

    I don't care what hardware you pimp, Microsoft. After your abusing everyone's privacy with your Windows 10 spyware, nothing you do matters anymore. Now go fuck yourself.

    signed
    former Microsoft fanboy

  3. DSPs by Jfetjunky · · Score: 5, Informative

    DSPs are special processors that generally have many dedicated multiplier cores, as well as other math functions implemented directly in hardware. This allows them to do things like fixed point math operations very fast, sometimes in as little as a single digit clock cycles neglecting pipeline delays. In some cases certain math intensive functions such as video encoding/decoding are implemented directly in hardware too for the same benefits.

  4. Awful article by klingens · · Score: 5, Informative

    This article is awful, both here on slashdot and pcworld. It shows that neither site is suitable for reporting on tech or IT journalism.

    TSM doesn't design chips, they build them. Others design the chips, hand over that design to TSMC to get actual hardware back. TheRegister correctly reports this "bult by TSMC"
    8MB SDRAM and 1GB DDR3 RAM. That is the same thing! DDR3 is a form of SDRAM and of course SDRAM makes no sense whatsoever here. Instead again, TheRegister correctly reports: 8GB SRAM, which is typically used for caching purposes: small size but fast, just like L1 to L3 caches in most/all CPUs which are also for caching.

    Neither slashdot nor pcworld senior editor can correctly transcribe a simple news tidbit from another site.