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AMD Declares Ryzen Will Be a Four-Year Architecture (extremetech.com)
An anonymous reader quotes a report from ExtremeTech : Having spent over four years designing the architecture, the company plans to keep it around for at least that long. That's according to CTO Mark Papermaster, who was on-hand to discuss the chip. First things first -- AMD is promising a hard launch for Ryzen, without any paper launches, limited availability, or limited product introductions. When Zen debuts it'll debut in multiple (still unknown) configurations, not a single eight-core part. As PCWorld details, Papermaster also confirmed the four-year target and emphasized that it didn't mean AMD wouldn't iterate the core. "We're not going tick-tock," Papermaster said. "Zen is going to be tock, tock, tock." There are several ways to read this sentence. Tick-tock refers to Intel's previous practice of introducing new CPU architectures in one product cycle and new manufacturing nodes in the other. AMD has never strictly deployed an equivalent approach over multiple product cycles. I wouldn't necessarily conclude that Papermaster is saying AMD won't deploy Zen on new manufacturing nodes over time, but that AMD intends to implement an aggressive series of tweaks and improvements to the current core as time goes by. There's a significant lag between when a design tapes out and when it ships to consumers. This means AMD's CPU design team is almost certainly hard at work on Zen's successor already, even though Zen hasn't actually shipped yet. While I can't make any concrete predictions about how Zen will compete against specific products in Intel's lineup, the demos we've seen and the product information already available has convinced me that Ryzen will be at least a meaningful and significant improvement on AMD's overall power efficiency, performance, and performance-per-watt.
Look, they're not going to do a paper launch, or ship vaporware, so they're not going to hype up the processor before you can buy the multiple configurations, at least one of which will have eight physical cores and be faster than some Intel processor. They showed benchmarks, they're talking up the marchitechture and particular configurations, what part of "no paper launch" don't you understand?
Give us real 8 cores with 8 FPU's. none of this cheap ass corner cutting. Intel has lost their way and you have a chance to become a real contender once again.
Your FPU wish is granted (sort of?). Two complete FPUs per core, implemented as two each parallel Fadd and Fmul units, capable of simultaneous scheduling and simultaneous floating point register access, per the detailed diagram here. The loader is 128 bits wide, so it does look like it can suck in, calculate, and shove out two 64 bit floating point instructions simultaneously, indefinitely, no bottleneck, with fancy dedicated instruction scheduling of its own.
As for 8 "real" cores (whatever a "real" core is these days), this makes mention of a "CPU Complex" of 4 cores. The implication being, you might see more than one CPU complex on the same chip. But that diagram should be telling you why Intel has been reluctant to give you 8 "real" cores. With four cores, your L3 cache already has to be 16-way associative to behave reasonably. You want to jam 4 more cores into that diagram. Looks like there's room, top and bottom, right? And double the cache size, to 16 MB. If you want it to behave as efficiently as the 4 core version, you're wanting 64-way associativity. Which is ridiculous, and probably doesn't scale as well as you'd hoped. What it sounds like AMD will be doing is plunking two of those CPU Complexes down side by side, then linking them to each other via the modern version of HyperTransport. The CPUs become ccNUMA within a single chip.
I'm afraid you're doomed to disappointment with Intel and AMD both. Without sandwich stacked circuits, building an L3 cache for 8 cores is just infeasible. You can fit all the transistors you need, but hooking them all together in a useful arrangement requires an absurd number of paths.