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Intel Supercharges Atom Chips With 16 Cores and Pro Level Features (pcworld.com)
Agam Shah, writing for PCWorld: Intel's Atom was mostly known as a low-end chip for mobile devices that underperformed. That may not be the case anymore. The latest Atom C3000 chips announced on Tuesday have up to 16 cores and are more sophisticated than ever. The chips are made for storage arrays, networking equipment, and internet of things devices. The new chips have features found mostly in server chips, including networking, virtualization, and error correction features. [...] A surprising feature in C3000 is RAS (reliability, availability, and serviceability) capabilities, which is mostly found on high-end Xeon chips. The feature corrects data errors on the fly and prevents networking and storage equipment from crashing.
Apple switching to 16-cores A16M ARM processors for their new Macs.
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These chips are designed for very parallelizable applications like file serving, managing multiple simultaneous VPN clients, etc. You want one core per NIC for these to make the best use of AESNI plus one or two more for management tasks.
Going from 16 to 4 would be a light version of the chip, and everyone knows that Cores Light is garbage.
W..w..W - Willy Waterloo washes Warren Wiggins who is washing Waldo Woo.
I have just finished building a pfSense firewall/proxy/router etc based on a PC Engines APU SOC. This has 4 AMD cores and 4 GB of RAM and is plenty powerful enough for what I need.
I guess 16 cores with all those extra bells and whistles would be nice for bigger customers than mine, but to be honest, the box I put together is plenty good enough, and the price was right.
Maybe the SME type market is not where Intel wants to play.
Can we have this in desktop processors too now, please? Bit errors in RAM are an underestimated source of data corruption and crashes.
Individual applications don't but open your task manager and look at how many processes are running. The more cores you have the more processing power the operating system has to distribute all those processes, and their threads, across. Furthermore some graphics programs and game engines sometimes use upwards of a dozen worker threads.
CPU power in general hasn't lept by great bounds in the last decade like it did 20 years ago when every new computer would be outdated in a year, so now the best strategy is to add more cores so each individual core isn't as burdened as it would otherwise be, and it will likely be the only strategy when we reach the limits of silicone based CPUs in the near future due to quantum tunneling unless someone comes up with something better. Stacking transistors could also be a possible solution sort of like a CPU skyscraper.
They'll just fill up more cores with @#&$% McAfee scans; they own half the company. It's like a dog breeding company also selling pooper-scoopers.
Table-ized A.I.
They'd like a spot at the table of the massive amount of chips that will be needed in autonomous cars and other AI driven machines. Parrelization works very well in processing data from lots of sensors. I suspect this is just the beginning.
Most people can't wrap their brains around more than two
Fortunately this is not a chip for most people, and boy are most people going to get upset if they look at their GPU.
, and most applications don't lend themselves to massive parallelization.
Actually a lot of the most computationally intensive tasks are embarrassingly parallel. But even if they aren't, who said we need to run one application per physical CPU? What version of DOS are you still running that doesn't allow multi-tasking?
Will these last longer than 18 months?
"You want one core per NIC for these to make the best use of AESNI plus one or two more for management tasks."
One Core per NIC? Given the drastically reduced connectivity in the C3000 versus even desktop Pentium line processors in the form of fewer PCI-E lanes, good luck getting one PCI-E lane per NIC, let alone one core per.
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
You might have a couple hundred tasks, threads or processes that sit there and collectively eat about 0.1% CPU time. Some are daemons waiting all day for you doing something that use them, some are GUI threads that similarly do nothing. They're like that guy who sits in a basement full of military archives and watches TV all day, only doing actual work for a couple minute once every week or month when someone comes to visit him.
I bet there are some people who have a touch screen laptop but don't know the screen can be touched.
They're like that guy who sits in a basement full of military archives and watches TV all day, only doing actual work for a couple minute once every week or month when someone comes to visit him.
Yeah, but he's really going to need them when he has to save America 500 years later with toilet water so it's better to have them and not need them than not having them in the first place.
Write and/or read. https://scifurz.wordpress.com/
I would be happy with a mini rack/blade system about the size of a HP MicroServer, with the ability to add 4-8 of these CPU boards in it as blades, each board having a SSD big enough to load a Linux distro or ESXi... and one has a nice CPU farm that doesn't take much space, but can run a lot of lightweight VMs very economically.
It's not just too many cores, it's too much everything. They've taken a crappy, underpowered chip that was trimmed to the bone to try and make something that competes with Arm, and are hacking on extras to make it sound more like a Xeon. In which case why not just use any non-Atom CPU, not necessarily a Xeon but just something that isn't as bare-bones as the Atom, and use that. Or an AMD G-series APU.
Or could this be Intel's trick, that they've taken a Core 2 Mobile CPU, scraped off the Penryn label, reprinted it as Atom++, and are shipping those?
No problem with touch screen laptops as long as they include a bag of cheetos.
love is just extroverted narcissism
You want one core per NIC for these to make the best use of AESNI plus one or two more for management tasks.
While we're talking about massive parallelity, I want Knights with NI.
Escher was the first MC and Giger invented the HR department.
They've taken a crappy, underpowered chip that was trimmed to the bone to try and make something that competes with Arm, and are hacking on extras to make it sound more like a Xeon.
So it's like taking Pentium 3 and hacking on extras from Pentium 4 (the actual innovations around the core, not the GHz race) to make Pentium M, then putting several of these on a single die to make the Core series? Not a bad idea.
Or could this be Intel's trick, that they've taken a Core 2 Mobile CPU, scraped off the Penryn label, reprinted it as Atom++, and are shipping those?
I think this already happened a while ago, in a way. For instance, the original Atoms didn't have out-of-order execution, but the later ones do: https://en.wikipedia.org/wiki/... It looks a bit like the Pentium brand that lives on as the low end of Cores.
BTW, I have one of the earlier in-order Atoms running happily in a server-ish machine where GPUs do all the heavy lifting. It's perfect for the job, and I guess more Atom cores would be great for a lot of server tasks, at least given enough I/O. Ideally, something like ARM or MIPS would probably be even better, but good luck finding (a) a suitable mobo with all the PCIe slots and (b) AMD/Nvidia binary drivers.
Escher was the first MC and Giger invented the HR department.
Virtual breasts, right?
So it's like taking Pentium 3 and hacking on extras from Pentium 4 (the actual innovations around the core, not the GHz race) to make Pentium M, then putting several of these on a single die to make the Core series?
It's not like that. It's like inventing a new execution unit primarily intended to preserve high margins on core architecture chips by delivering substantially worse superscalar performance. Billed as power efficient, the latest generation with out of order execution still delivers worse performance at the low power end then celerons. It's a scam. Intel knows what to do to make Atom not suck: just throw it away and use core arch. But the charade is going to continue as long as Intel is able to avoid serious competition with its high margin parts.
When all you have is a hammer, every problem starts to look like a thumb.
Be careful asking for that. They may require a shrubbery.
- Mike
16 is about 12 too many. Most people can't wrap their brains around more than two, and most applications don't lend themselves to massive parallelization.
The thing I'm not getting is: is the Atom supposed to be a low power chip, or a low cost chip? I don't see how either of them is satisfied by blowing things up to 16 cores.
hope they fixed the clock issues plaguing the C2000 !
Embedded/ultra low power CPUs is where Intel does have serious competition. It's the desktop arena where they have a virtual monopoly.
Yes, and they keep trying to push crappy Atom parts into that market segment to avoid cutting margin on their low power celerons, which are better than Atoms by every measure including power consumption. I thought I already said that?
When all you have is a hammer, every problem starts to look like a thumb.
Going from 16 to 4 would be a light version of the chip, and everyone knows that Cores Light is garbage.
I never drank Coors light.,
Leslie Satenstein Montreal Quebec Canada
DIrect comparison (mips * clock frequency) is not a true measure.
There was a posting that doubted AMDs performance against equivalent Intel chips. The author used a frequency * mips rate to indicate throughput.
Here are some explanations about the difference between Ryzen and older CPU chip techolologies.
How to explain the difference? Here is my take. First of all, a 3 ghz frequency means that there are usually 6gig of clock ticks. Some instructions take multiple clock ticks. When cpus are implemented on 14nm cell sizes, there is room within the die for many many more cells. Cells that could be used to do things better.
For example , suppose that a “long integer” multiply/divide requires 20+ clock ticks with one model CPU, and because of design improvements and cell size reductions, the same operation on the Ryzen may only require 16+ clock ticks. That instruction’s execution is improved by 20%.
Consider parallel operations within the cpu chip. To achieve more parallelism, you need to allocate more logic to the multiplier/divider circuitry. And that is probably what has happened. (Smaller micro-circuit sizes allows more logic space available within the CPU die).
You bought a 16core cpu chip. Ask yourself how many internal (additional reserved) cores are present within the chip for the chip to do it’s work? These reserved cores could be working in parallel to implement an instruction, thus completing a complex instruction in fewer clock ticks. (AES encrypt)
Go through all the instructions that can be optimized by smarter circuitry, and you have the explanation why the AMD chips are more performing than ever.
If there are more logic elements, then consider that a “register” shift instruction could be optimized to three or four clock ticks, irrespective of the shift amount. Typically, the shifter hardware moves the bits, according to a specified amount.
I am willing to bet that chip for chip, the AMD has many more transistors and gates for logic to support parallel sub-instruction processing than found in older designs. More parallelism used to support fewer clock-ticks.
Instructions within a CPU are also within a pipeline queue. I do not know the chip internals, but there may be up to 10+ instructions in the input queue that are at various stages of being decoded. The queue is flushed if an interrupt instruction is received.
Taken all together, fewer clock ticks to decode an instruction, perhaps saving some of the queue contents during an interrupt may be the major reason the AMD chips even with slower clock frequencies are faster than older chip designs. Older designs need to boost clock speeds by up to 25% over the AMD chips, to arrive at par.
There was a posting that doubted AMDs performance against equivalent Intel chips.
Here are some additional explanations about the difference. How to explain the difference ?
Here is my take. First of all, a 3 ghz frequency means that there are usually 6gig of clock ticks. Some instructions take multiple clock ticks. When cpus are implemented on 14nm cell sizes, there is room within the die for many many more cells. Cells that could be set aside to do things better.
For example , suppose that a “long integer” multiply/divide requires 20+ clock ticks with one model CPU, and because of design improvements and cell size reductions, the same operation on the Ryzen may only require 16+ clock ticks. That instruction’s execution is improved by 20%.
Consider parallel operations within the cpu chip. To achieve more parallelism, you need to allocate more logic to the multiplier/divider circuitry. And that is probably what has happened. (Smaller micro-circuit sizes allows more logic space available within the CPU die).
You bought a 16core cpu chip. Ask yourself how many internal (additional reserved) cores are present within the chip for the chip to do it’s work? These reserved cores could be working in parallel to implement an in
Leslie Satenstein Montreal Quebec Canada