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Startup Offers A Chip Based On The Open Source RISC-V Architecture (computerworld.com.au)
angry tapir shared this news from Computerworld:
An open-source chip project is out to break the dominance of proprietary chips offered by Intel, AMD, and ARM... A startup called SiFive is the first to make a business out of the [open source] RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed... but the company will not charge royalties. That makes it attractive alternative compared to chip designs from ARM and Imagination Technologies, which charge licensing fees and royalties.
One of RISC-V's inventors co-founded the company, and he says that support is growing -- pointing out that there's already a fork of Linux for RISC-V.
One of RISC-V's inventors co-founded the company, and he says that support is growing -- pointing out that there's already a fork of Linux for RISC-V.
But you have to pay a shitton of money to get the license. Well a shitton to a regular person anyway. If you can afford to manufacture one of these chips the license cost is probably a drop in the bucket.
I see you've been courted by ARM's marketing department. They've been coming to us as well with exciting charts about how affordable ARM licensing is versus the evil expensive RISC-V. But look closely, it's bullocks.
If all you want to do is mark Cortex-M0 chips, then ARM's DesignStart license is cheaper than hiring an engineer to put together a RISC-V. ($40K iirc). Of course ARM makes that up if you manage to ship a lot of M0 units. But if you need a wide range of ARM products, the licenses quickly get more expensive. And sadly ARM's marketing department doesn't tell you their top tier license is 20x more than their bottom end.
Anyone can produce a RISC-V. But you can pay these guys to have a ready to synthesize solution.
There is a free open source version, and it looks pretty good. But the free one (E310) is not going to have all of those extra bus interfaces. That makes it difficult to connect to high speed peripherals or have operate in a multiprocessor environment (especially SMP).
Ultimately SiFive is operating a business that serves other businesses, not end users. The licensing of IP is the classic (and safest) way to operate a fabless silicon business.
Nothing is preventing you from making your own RISC-V from scratch. Unlike something like ARM where you have to pay them fees to cover patents and trademark even if you don't use ARM's implementation. And honestly it's cheaper to license ARM's implementations than to get permission to make your own. With RISC-V the opposite is true, it's free to make your own or you can pay money to license from multiple companies, who hopefully compete with one another or differentiate in other ways.
“Common sense is not so common.” — Voltaire
If only there was this way to program a gate array in the field.
This is about security. Cost is second. If I can implement an open source RISC-V processor, don't you get that I could audit every instruction executed, as well as the means to execute those instructions? Most people blindly support a black box known as Intel or AMD to execute their instructions. There could be a dozen things undocumented hiding in that box that you never knew about, whether planted there unintentionally as bugs, or intentionally by governments and large companies.
Did you even look at their website or the product manual? It's already designed around a 64 bit core.
https://www.sifive.com/documentation/coreplex/e51-coreplex-manual/
RISC-V can be embedded into your ASIC design, which is not something you can do with an x86-64 from Intel or AMD. Not only because RISC-V tends to be smaller, but because Intel and AMD do not license their designs in such a way to allow vendors to embed the design. The other aspect or RISC-V that I think is quite interesting is that it has a wide range of configurations, allowing you to tailor an instance of the processor for your particular application.
I expect in the near future you will see RISC-V popping up as embedded processors in cameras, TVs, smart appliances, cars, routers, and more. Places where you might have had a MIPS or ARM in the past could also be serviced by a RISC-V. And the configurations available are quite a bit more flexible than MIPS and quite a bit cheaper than ARM, making it fit a broad range of markets. In a few years you will likely be using a RISC-V in some way, even if you are still stuck on trying to force your comparisons to a narrow market of desktop PCs. (your PC's GPU will probably have one or more RISC-V cores on it to manage power and orchestrate jobs to shaders)
Price and flexibility is the advantage here. Power is basically a solved problem, we know theoretically what the best power we can achieve for a particular computation (thanks to the laws of thermodynamics), and at a very low level that is already done by all the low power architectures, including x86. Theoretically RISC-V is as scalable as any other modern CPU architecture, and maybe someone will make a super computer out of the 64-bit variant of it some day.
“Common sense is not so common.” — Voltaire
Both CISC and RISC translate to an internal CPU microcode. The difference is that the RISC translation is generally much simpler requiring a smaller portion of the CPU die. But as CPUs get larger, this difference becomes less relevant when looking at the overall CPU.
There are no real advantages to CISC. One used to be able to argue that the required instructions are more compact but ARM CPUs demonstrated how a similar effect can be accomplished with their Thumb2 instructions. But there are also no longer any real disadvantages to CISC either - at least with reference to larger PC class CPUs.
So it comes down to backwards compatibility with existing software - the real reason why most of our desktops are currently powered by a CISC architecture.
To embed an x86 into an ASIC without permission from Intel you'd have to choose one that is not patent encumbered, so a 20 year old architecture would theoretically be possible. Starting this year(2017) you could do a Pentium II or Pentium Pro, which is not too shabby really. If you took the original masks, you could start right away, but the process differences may be difficult to resolve and you'd be saddled with a bus architecture that is incompatible with the rest of your ASIC's IP. And starting from scratch in HDL would mean you'd be writing your own verification suite, not impossible but a lot of work. But RISC-V and ARM already give you much of the CPU verification that you need.
It all boils down to money. Spend money licensing a modern RISC, or spend money recreating a 20 year old variant of x86 that carefully avoids patent infringement. One of those seems like a good business strategy, the other does not.
(yes, I'm in the chip industry. So this isn't really just armchair hobby stuff to me)
“Common sense is not so common.” — Voltaire
the Tensilica Xtensa CPU which is the bit with the ARM license
The Tensilica CPU is not an ARM. It is presumably cheaper, but not free, and which burdens them with the cost of learning a relatively unknown CPU architecture. If you're going to take that cost, you might as well drop in a RISC-V core, and pay nothing, plus you get to benefit from the growing open source infrastructure around it.
Now compare that with the cost of fabbing your own RISC-V
The company that makes the ESP8266 is already fabbing the SoC, so there is no extra cost for the RISC-V.
it's not competing with the hundredth-of-a-cent licensing costs per ARM core shipped,
ARM charges 1.2% of the chip price for a Cortex. So, for a $1 chip, that's 1.2 cents. May not seem like a huge deal to you, but apparently it mattered enough not to get an ARM.
That's not needed since Pentium patents expired.
Great, now where can I get the HDL sources to embed a Pentium in my own ASIC ? Or, are you suggesting that I can just clone a Pentium myself ?
unless they can magic the masks and other components out of nothing, the cost of creating RISC-V stuff is going to be considerable
Not really. They are already making ASICs with their own stuff. And those ASICs already have a core of some sort. Taking out the HDL from the core, and inserting other HDL for another core, doesn't really change anything in their process. A CPU core is relatively simple piece to synthesise, all straight digital CMOS with standard library components.
If and you're starting with a new ASIC, it's even easier to pick a free core from the beginning. And when you're doing a second ASIC based on the same core, it's almost no work at all.
...there's already a fork of Linux for RISC-V.
Wrong approach.
The right approach is to take FreeBSD who's upstream is already mature on RISC-V and you don't have to go to look for patches.