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Upcoming USB 3.2 Specification Will Double Data Rates Using Existing Cables (macrumors.com)
A new USB specification has been introduced today by the USB 3.0 Promoter Group, which is comprised of Apple, HP, Intel, Microsoft, and other companies. The new USB 3.2 specification will replace the existing 3.1 specification and will double data rates to 20Gbps using new wires available if your device embraces the newest USB hardware. Mac Rumors reports: An incremental update, USB 3.2 is designed to define multi-lane operation for USB 3.2 hosts and devices. USB Type-C cables already support multi-lane operation, and with USB 3.2, hosts and devices can be created as multi-lane solutions, allowing for either two lanes of 5Gb/s or two lanes of 10Gb/s operation. With support for two lanes of 10Gb/s transfer speeds, performance is essentially doubled over existing USB-C cables. As an example, the USB Promoter Group says a USB 3.2 host connected to a USB 3.2 storage device will be capable of 2GB/sec data transfer performance over a USB-C cable certified for USB SuperSpeed 10Gb/s USB 3.1, while also remaining backwards compatible with earlier USB devices. Along with two-lane operation, USB 3.2 continues to use SuperSpeed USB layer data rates and encoding techniques and will introduce a minor update to hub specifications for seamless transitions between single and two-lane operation.
The difference is that the data on each line is sent serially, with embedded clocking and controlled skew between lanes- meaning that the data on each lane is somewhat independent. In general a parallel bus includes separate clocking. In a serial bus like this, the data is encoded in certain ways to allow the clock to be a part of the data- the most basic encoding is what is used in 10Mb Ethernet- Manchester, where every bit has it's own clock, and it goes up from there.
No it's the right direction providing they get to the correct end goal. We're in a transition period where the capability of the spec is being built up. The end goal is perfectly in line with what you are saying: one plug, do everything, no confusion.
It's just not there yet.
It's harder than you think: as you increase the data rate, trying to synchronize all 8/16/32/whatever lines becomes close to impossible. Breaking the data into multibit chunks and sending each serially via a different channel is easier because each channel can run independently, without regard to latency.
I believe this type of thing is also why we've moved away from, say, CPUs with direct access to memory (instead CPUs have multiple layers of cache between them and the computer's real memory.) It'd be nice and much more efficient to have the memory in your computer deliver up 64 bit words to the CPU at 4 gigawords a second (ie in sync with the CPU's 4GHz clock), but good luck trying to make a parallel motherboard bus that can deliver that.
You are not alone. This is not normal. None of this is normal.