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The Secret to Tech's Next Big Breakthroughs? Stacking Chips (wsj.com)
Christopher Mims, writing for the Wall Street Journal: A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes (Editor's note: the link could be paywalled). Chip designers -- now playing with depth, not just length and width -- are discovering a variety of unexpected dividends in performance, power consumption and capabilities. Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera. Think of this 3-D stacking as urban planning. Without it, you have sprawl -- microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
This was thought of a long time ago and experimented with, but the real problem with it was heat.
No, it wasn't. You can run them at lower power and therefore generate less heat. The issue is that lithographic techniques don't let you get more than a few layers thick before the negative f-theta lenses employed are out of focus. You end up needing nano-positioning stages along the Z-axis, which as a matter of necessity means you need nano-positioning stages along at least 3 corners of a wafer, and along the X/Y (separate from the galvanometers or nanoactuated mirrors behind the negative f-theta lens) in order to keep the wafer aligned in the plane projected by the negative f-theta lens (just forget about doing this stuff with masks without using similarly complex alignment methods on both the wafer and the mask holder.)
The real 'breakthrough' and 'innovation' is being down to the 10nm scale, and other lower-power options, enabling silicon to run cooler yet at faster speeds.
No, it isn't. Scaling down allows you to run at lower power for higher frequencies, but you could just as easily reduce the frequency of the chip to spend less power. You end up getting less out of it, but not in terms of FLOPS/Watt - it's just that we focus on the FLOPS aspect more than the Wattage. Scaling along the Z axis has been the issue for a long time, you just can't do it with things in the nanometer range without absurdly complex chip fabrication equipment and effectively building 1 chip at a time (with a lithographic mask you can make hundreds or thousands of ICs at the same time because the Z axis changes relatively little across the X and Y axis, but when you're talking about building a little tower suddenly you have to deal with a host of changes.) To use the building analogy: you can tilt a 1-story building 5, even 15 degrees, and still drop a rock above a room to land on the roof of that room without knowing anything beyond the X and Y coordinate of the room relative to the floorplan - if you try the same thing on the 40th floor of a skyscraper tilted at even 1 degree you aren't going to be anywhere near it, you'll just hit an exterior wall several stories down.