Intel CPUs Vulnerable To New 'BranchScope' Attack (securityweek.com)
wiredmikey writes: Researchers have discovered a new side-channel attack method dubbed "BranchScope" that can be launched against devices with Intel processors. The attack has been identified and demonstrated by a team of researchers, and similar to Meltdown and Spectre, can be exploited by an attacker to obtain potentially sensitive information they normally would not be able to access directly. The attacker needs to have access to the targeted system and they must be able to execute arbitrary code.
Researchers believe the requirements for such an attack are realistic, making it a serious threat to modern computers, "on par with other side-channel attacks." The BranchScope attack has been demonstrated on devices with three types of Intel i5 and i7 CPUs based on Skylake, Haswell and Sandy Bridge microarchitectures. Further reading: As predicted, more branch prediction processor attacks are discovered (ArsTechnica).
Researchers believe the requirements for such an attack are realistic, making it a serious threat to modern computers, "on par with other side-channel attacks." The BranchScope attack has been demonstrated on devices with three types of Intel i5 and i7 CPUs based on Skylake, Haswell and Sandy Bridge microarchitectures. Further reading: As predicted, more branch prediction processor attacks are discovered (ArsTechnica).
Every vulnerability needs a HYPED UP MARKETING NAME in the TECHSOCIAL INDUSTRY!!
EVERYTHING ABOUT TECH IS SOCIAL!!!!
Nerds who built all our technology, die in a fire. We the Social don't need nerds anymore.
I'll pencil this one in as "yet another Intel patch I won't be applying in 2018"
When the poo hit the AMD fan a few weeks ago it was front page news everywhere, but now that it has been slung back at Intel, it's good to see Ars is not making this article front and center, but rather downplaying it a bit. I actually had to search the front page to find it.
Only if it's the low power, low performance versions with no out of order execution.
You could also go with Intel Atom
VMs are safe they said
You can't break out of your sandbox they said
"The attacker needs to have access to the targeted system and they must be able to execute arbitrary code."
Non-news. Move along.
Correction #1: "...pile of leaks that should worry people."
#2: "I have a thing for asterisks."
Friggen Mondays. (I was off yesterday, so it's a mental monday.)
Table-ized A.I.
can be exploited by an attacker to obtain potentially sensitive information
In other words, there is a one in a billion chance that an attacker would obtain something of importance.
Not in the given citation. Potentially means potentially, nothing more, nothing less.
The attacker needs to have access to the targeted system and they must be able to execute arbitrary code
In other words, a completely worthless exploit.
Getting arbitrary user code running is relatively easy and any exploit that can bypass any kind of protection from a user mode program is a real problem.
So two out of two wrong. Better luck next time!
Although I expect Intel to correct that.
This all depends on what "access" means. If it means browser drive-by, then it's quite dangerous. If it means physical access, then it's trivial.
I think we've pushed this "anyone can grow up to be president" thing too far.
IIUC, it's only the older models of the Atom that are safe. The more recent models have the same flaw.
I think we've pushed this "anyone can grow up to be president" thing too far.
It's not trivial if it spans VMs, and one client of a hosting service can eavesdrop on another via this side channel. That has been the fear with Spectre and Meltdown, and it is most likely the fear here as well.
How is the Riemann zeta function like Trump rallies? Both have an endless number of trivial zeros.
Another day, another Intel CPU vulnerability revealed. I'm beginning to wonder if we wouldn't all be better off using Motorola chips.
___
"Second place is first loser," whined the second loser, the third loser, the fourth loser... etc., mistakenly thinking they were being clever.
There is no justice ... ... death is the only answer
Another consultant who stuck it out.
"We are the Priests, of the Temples of Syrinx..."
AMD needs to have ryzen pro with ipmi (like Intel xeon-e3) and ThreadRipper boards (Xeon W).
Cue up another " hotfix " that will be deployed half a dozen times before it's ready to screw things up again. :|
My condolences in advance if you're running Windows 10 and the unstoppable update machine
SERENITY NOW!
#DeleteFacebook
Yeah after all those security problems, I'm almost expecting Apple to launch a new A10-powered laptop real soon now (TM).
#DeleteFacebook
It would be nice if they had worked with vendors to disclose this before publishing it. ... or did I miss that?
can be exploited by an attacker to obtain potentially sensitive information
In other words, there is a one in a billion chance that an attacker would obtain something of importance.
Yes, and when you have the computing power at your disposal to make billions of attempts per second it doesn't really take long at all.
Citation please. TFA doesn't even clarify what "access" means in this case.
First create a CPU core with a low level core for the base OS
Kind of like Intel management engine running Minix...
Amen.
You've got me. It's an interesting question. OTOH, there are supposedly a lot of known ways of accessing the host computer from the VM, and perhaps those don't require out-of-order execution to implement.
I think we've pushed this "anyone can grow up to be president" thing too far.
Now you know why INTeL was always faster than AMD... they cut corners where they shouldn't have.
can the code running on that emulated cpu achieve any of these out-of-order execution exploits against the host cpu running the emulator software?
It depends on the depth of the pipeline of the CPU.
If it long enough, the physical CPU might speculatively execute past the point where Qemu simulated the check in the emulated CPU, up to the point where Qemu simulate the payload that the attacker are wanting the emulated CPU to execute.
The thing is, for performance reason, if everybody switches to emulated CPUs (Java's / .NET's dreams), that's exactly the direction we will be heading onto :
- CPU getting longer pipeline (yet again, just like old P4) to try to squeeze more performance
- emulator getting more efficient at simulating the CPU.
Worse part ?
On intel architecture, that's already the case sometimes : Google's project zero managed to exactly pull this situation off, by running eBPF bytecodes (bytecode used by the programmable packet filtering virtual machine) on a few select Intel hardware.
(On AMD, the same only work when JITing is activated, otherwise the speculative execution doesn't reach far enough).
"Sufficiently advanced satire is indistinguishable from reality." - [Tips: 1DrYakQDKCQ6y52z6QbnkxHXAocMZJE61o ]
Nope, there's not.
Technically the processors don't even belong to the customers. Intel still maintains full control over them, granting their buyers/users only very little of the same.
Unfortunately they also give full control over your management engine to others, if they want to. This machine (running MINIX on a power-efficient core) can then do - literally - anything behind your back, as you have no possibility to check what it is doing (which is exactly the way they want it to be)...
It wouldn't be a terrible idea if it was open, and user(admin) accessible/configurable.
"Prediction: within 10 years, Windows will be a Linux distribution." Me, 7-6-2016
X86 isn't that bad. It's easier to decode than many other architectures, it's easier to make superscalar than many others, it support extensions of the instruction set. The last one is why we are still using x86.
X86 processors execute x86 instructions. They are x86 and only a subset of instructions aren't executed directly. There is no translation hardware unless you call the instruction decoding translation (technically correct) and then almost every processor made have/had translation hardware.
Instruction fusion? Used on RISC. Instruction splitting? Used on RISC. Detection of special cases? Used on RISC (e.g. r0 or r31 defined as zero). Those are all optimization tricks.
Another reason to not use VMs or cloud technologies on machines you do not directly control.
SJW: a person who perceives an injustice, and while correcting it, commits a greater injustice.
I disagree the cloud is inherently less secure than the traditional approach. If one gives their "local" equipment and setups decent tender-loving-care, yes it's more secure than the cloud, but the average user won't bother, including many businesses.
The "problem" with the cloud is similar to nuclear power generation. Technically its record is safer than the alternatives. However, its failures make big news, which skews perceptions and fears. (Gas and coal kill through cancer and other ailments, and over time the total deaths far exceeds deaths related to nuclear power plant accidents.)
Therefore, the cloud has a PR problem, not so much a technical problem when it comes to security. It's not perfect by any stretch, but will probably be statistically better than the alternatives. But being statistically better may not be enough.
Table-ized A.I.
-1 = no sense of humor.
I don't believe in karma, I just call it like I see it.
No one agreed with you the first 100 times you've said this. Give it a rest.
If i have access and can run arbitrary code then I can do whatever on that computer.......... so this isn't really a vulnerability..
Yes but the mess is due to its longevity! Remember we are talking about an architecture released in the 70's and now being 40 years old.
Core instructions aren't outdated with a few exceptions (when designing AMD64 some old instructions were removed and some reused), some instructions aren't used much anymore but are similar and execute in the same execution units as new extensions, some are just supported but not optimized for.
Compare with the original ARM instruction set which was released later but have had more incompatible extensions (reusing the same instruction encoding) and even a very incompatible change to extend the address space.
I don't claim it's a beautiful design or that there aren't better ones just that it isn't too bad.
--
The main problem with x86 isn't decoding but finding the start/end of internal fields.
[0-x prefixes] [op] [R/M] [SIB] [disp] [imm]
([op] can also be a [0xf] [op] in processors after the 8086/8088 for extended instructions)
[0-x prefixes] [REX prefix] [op] [R/M] [SIB] [disp] [imm]
REX is a special prefix added with AMD64.
[0-x prefixes] [VEX prefix] [2|3 extension field] [op] [R/M] [SIB] [disp] [imm]
SIB field is available for certain R/M encodings, added with the 386.
x+rest of the instruction 15 bytes (maximum instruction length)
You have to admit that the x86 32-bit processors where really only 16-bit processors by design. They were about ten years behind when they got 'elected' by IBM.
;-)
With AMD64 the situation has improved. They look more like 32-bit processors nowadays.
About every year we had some extensions, which became obsolete a year-and-a-half later. The result of this policy is that most software doesn't make use of those 'nifty' extensions.
We are seeing now that Intel cheated. They did cut corners, and they did run red lights. They looked at the MMU as if it were a zit they could simply ignore while shaving. Meltdown cuts down the performance significantly. More appears to be coming.
I'm exited to find out how much will be revealed in the end. If it rains down badly, all those processors will only be usable in single-user systems. MS-DOS is calling...
No, access to a neighboring VM is sufficient. You can get that fairly cheap in the cloud.