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Intel: We 'Forgot' To Mention 28-Core, 5GHz CPU Demo Was Overclocked (tomshardware.com)

Posted by BeauHD on from the how-convenient dept.

At Computex earlier this week, Intel showed off a 28-core processor running at 5GHz, implying that it would be a shipping chip with a 5.0GHz stock speed. Unfortunately, as Tom's Hardware reports, "it turns out that Intel overclocked the 28-core processor to such an extreme that it required a one-horsepower industrial water chiller." From the report: We met with the company last night, and while Intel didn't provide many details, a company representative explained to us that "in the excitement of the moment," the company merely "forgot" to tell the crowd that it had overclocked the system. Intel also said it isn't targeting the gaming crowd with the new chip. The presentation did take place in front of a crowd of roughly a hundred journalists and a few thousand others, not to mention a global livestream with untold numbers watching live, so perhaps nerves came into play. In the end, Intel claims the whole fiasco is merely the result of a flubbed recitation of pre-scripted lines, with the accidental omission of a single word: "Overclocked." Maybe that's the truth, but there's a lot of room for debate considering how convenient an omission this is.

28 of 165 comments (clear)

  1. Really? by orlanz · · Score: 5, Insightful

    I was pretty sure it was way overclocked. Kind of thought it was obvious. They aren't working on anything in the 4GHz range so why would they suddenly jump to 5 for release?

    1. Re:Really? by Narcocide · · Score: 5, Insightful

      Pointy-haired bosses will nonetheless believe this is what they're getting when they buy their next round of office desktops without even considering AMD solutions.

    2. Re:Really? by iggymanz · · Score: 5, Interesting

      well IBM power8 has 5GHz chip, what's Intel's problem

    3. Re:Really? by edwdig · · Score: 2

      They demoed the system in public. The case was open. There were large pipes running into it for the water cooling, and a large water chiller unit next to it. There were pictures of the setup included in the initial articles about it.

      They didn't explicitly state that it was overclocked because it couldn't possibly be more obvious.

    4. Re: Really? by jimbo · · Score: 2

      Intel tried with the i860 which was launched with great fanfare and became a huge failure. Later they tried again with the Itanium which actually reused some of the i860 marketing material and also failed, though it did manage to indirectly kill some competing architectures, like HP PA RISC and Digital Alpha.

      Part of the reason for Intel failing with Itanium was AMD64 which was easy to deploy and in fact turned out to perform very well. It might be an ugly instructionset but it seems to have trivial impact. Perhaps it is a different story on very low power systems (ARM).

    5. Re:Really? by Anonymous Coward · · Score: 3, Insightful

      Maybe because it is unknown how long this system will be stable? You know - You can drive electronic devices like processors beyond their limits for a certain time, but operating all time beyond limits shortens the life expectancy dramatically. On top of that, the number of hardware faults will also increase. You certainly do not want to have that that in production/reliable environments.

      And third (and this is important) - If they do such a thing, it is obvious they choose a "perfect" sample from the batch, but it is very likely that "standard" users will get an average processor, that will never reach that performance. In that sense it is completely misleading. They present something that a "standard" user is not able to do, even if they use above normal cooling.

      Intel used this misleading presentation in hopes it will "stuck" in the brains of the decision makers, even after they admit they represented a false image of performance. In my opinion Intel is scared that the AMD upcoming processors take a bite out of their market, and goes for this kind of misleading stuff to keep their hold.

    6. Re:Really? by Rockoon · · Score: 2

      As far i know, this translator is actually quite tiny.

      Not only is it tiny, its a necessary thing for chips to approach optimality that they have instructions that produce more than one "minimalist" operation. The rate that they could feed the execution units on pure RISC chips was THE bottleneck, and probably still is, that keeps RISC from winning the performance game.

      It isnt just the lack of read-modify-write instructions either, but it is a fine example of the RISC problem. On x86 an instruction like "add [dword ptr address], eax" is turned into 3 uops within the decoder that are equivalent to a RISCy implementation of the 3 inherent "simple" operation. The thing is the RISCy version requires 3 times as much instruction fetch as the x86 equivalent.

      During the height of the RISC vs CISC war, processors were limited to 8 bytes of bandwidth per clock cycle for the instruction fetcher while at the same time were introducing "super scaler" features. If you wanted your architecture to execute 2 operations per clock cycle, then it had better be able to fit their encoding into the 8 bytes of the fetcher. In this example RISC requires that the address be stated twice in the instruction stream and that alone is already 8 bytes for 32-bit systems. The read-modify-write x86 equivalent only requires that the address be stated once, AND ALSO only needs to encode 1 instruction. So on x86 the 3 operations could be pipelined in one cycle with instruction bandwidth to spare while on say ALPHA it required multiple cycles due to its instruction fetch bottleneck.

      RISC is a label for one of the extreme ends of architecture design, and its not optimal. Nobody is doing the other extreme end, which also isn't optimal.

      --
      "His name was James Damore."
    7. Re: Really? by Rockoon · · Score: 3, Insightful

      RISC is a solution looking for a problem at this point. While you dont need a complicated decoder on RISC, If you want to perform as well as x86 while being RISCy then you need more instruction fetch bandwidth going into the decoder than x86 needs. Its a tradeoff that does not favor RISC, which is why it lost. RISC was winning up until the moment that CPU's went super-scaler, at which point the instruction fetch shortcoming becomes a losing burden.

      --
      "His name was James Damore."
    8. Re:Really? by TheRaven64 · · Score: 2

      It's a bit more subtle than that. Since about 2007, we've not been seeing Dennard scaling, so although transistor counts have gone up, the number that you can power at any given time has not increased by nearly as much. This is what people mean when they talk about 'dark silicon'. The problem with the x86 decoder is that it needs to be powered most of the time, because any time you're executing instructions that are not in the trace cache, it's necessary. The same is true for caches (though you can turn off some of the ways in a set-associative cache when you're seeing that they're not used - not sure if anyone does this in commercial processors) and the register rename engine. All of the execution pipelines can be power gated so you can turn some of them off depending on the instruction mix (for example, powering down the AVX pipes in scalar workloads).

      It doesn't matter much to Intel at the high end, because it isn't a huge part of the total power consumption, but it is a problem at the low end when reducing the power consumption of everything else makes it start to dominate again.

      --
      I am TheRaven on Soylent News
    9. Re:Really? by Megol · · Score: 2

      Simple: overclocked = clocked higher than specified as the normal operating range. Specified is the important part.

      So if Intel said that their processor could run at 5GHz when kept at (let's say) 20 degrees Celsius maximum and still be within specifications it wouldn't be overclocked.

      That's what everyone was thinking this was about, cherry picked processors from the very top bin deemed reliable if coupled to some extreme cooling system.
      The difference here is that Intel failed to mention that despite their heroic cooling efforts the system wasn't guaranteed to actually work at that clock speed.

      Not obvious to me at least. And very dishonest _even_ if the presenter was expected to scream of the top of his lungs that the system was overclocked.

    10. Re: Really? by dgatwood · · Score: 3, Interesting

      RISC is a solution looking for a problem at this point. While you dont need a complicated decoder on RISC, If you want to perform as well as x86 while being RISCy then you need more instruction fetch bandwidth going into the decoder than x86 needs. Its a tradeoff that does not favor RISC, which is why it lost. RISC was winning up until the moment that CPU's went super-scaler, at which point the instruction fetch shortcoming becomes a losing burden.

      Not at all true. RISC didn't lose. PowerPC lost because Apple didn't have the marketshare to be worth IBM's time. IBM wanted to focus on building hardware for gaming consoles where they thought they could get better volume, and didn't want to spend the R&D effort to build a version of the G5 that could thermally survive in a laptop. The gaming console designs mostly paired lots of DSP hardware with a really minimal (603e-quality) main core, so those designs were unsuitable for Apple's needs.

      But RISC itself has basically won at this point. The most popular CPU architecture on the planet, by a large margin, is ARM, which is RISC. There are on the order of 250 times as many ARM chips built every year as x86/x86-64 chips from AMD and Intel combined. Pretty much every cell phone out there uses the ARM ISA, and more and more tablets are switching to ARM every year. Why? Because CISC doesn't scale nearly as well as RISC in terms of CPU horsepower per unit heat/power, which is the most critical thing for mobile devices, laptops, etc.

      I expect CISC to be basically dead in twenty years, and possibly sooner.

      --

      Check out my sci-fi/humor trilogy at PatriotsBooks.

    11. Re: Really? by edwdig · · Score: 2

      Because CISC doesn't scale nearly as well as RISC in terms of CPU horsepower per unit heat/power

      What you're seeing has nothing to do with CISC vs RISC and everything to do with the design philosophy behind x86 and ARM.

      x86 chips were designed for decades to favor raw power over efficiency. ARM was designed from the start to optimize for power efficiency.

      Any time you add a feature or an optimization to a chip, the designers ask if it's worth the cost both in terms of transistors required and power usage. Intel focused on chips running off wall power that sold for hundreds of dollars, so it was generally pretty easy to justify adding things. ARM focused on chips that cost tens of dollars and had to run off small batteries. Features don't get added to ARM chips unless they add a lot of performance for the transistor/power cost.

      If you look at Power or Sparc instead of x86, you'll find similar results. If anything, those RISC chips are probably even more power inefficient, as they were designed for customers who demanded top of the line performance and were willing to pay a lot for it.

  2. And it was a 32 core machine ... by perpenso · · Score: 4, Funny

    We 'Forgot' To Mention 28-Core, 5GHz CPU Demo Was Overclocked

    They probably also forgot to mention that it was a 32-core device with 4 faulty cores. ;-)

    1. Re:And it was a 32 core machine ... by Ecuador · · Score: 2

      And that you can't use it to divide floating point numbers if you care about the accuracy of the result ;)

      --
      Violence is the last refuge of the incompetent. Polar Scope Align for iOS
    2. Re:And it was a 32 core machine ... by alvinrod · · Score: 4, Informative

      I would have assumed this was the case as well, but this is almost certainly one of their Skylake XCC (Extreme Core Count) chips that are used for the high-end Xeon processors that retail for around $10,000 depending on clock speeds. The cores are laid out on a 5 x 6 grid, but two of the spots are used for the memory controller. Here's a site with a good shot of the die and a diagram of the parts of the chip.

      I don't know what they intend to charge for this thing, but it's a full chip and utterly massive at almost 700 mm^2. I don't expect it to normally run anywhere close to 5 GHz as one of the tech sites pointed out that Intel was using a stand alone water cooler rated for about ~1700W and that the power supply for their demo was a 1600W job, but even having 28 cores at 3.5 GHz is an insane amount of computational power. I expect it to be priced similarly.

    3. Re:And it was a 32 core machine ... by Ramze · · Score: 3, Insightful

      This wasn't a new chip -- it was a rebranded server chip overclocked to 5 Ghz using external -10 C (14 F) temp cooling system and a modified motherboard that could use non-ECC memory.

      No one would seriously purchase that abomination. It was meant as a distraction and a bit of marketing to compete with AMD's upcoming 32 core Threadripper 2 that was announced shortly after. It was literally a "hey, we got something that can compete with that!" pony show where no one talked about the cooling system needed to overclock it that high -- or even that it was overclocked. Inexperienced reporters ran with a headline that this was a new desktop CPU we might be seeing in the near future. Nope.

      They are already now fessing up that if this thing sees daylight, it won't be stock clocked to 5 Ghz -- you'd be lucky to see it at 3.7 Ghz with boost to 4.2 Ghz on some cores. It's literally nothing new and worse than AMD's threadripper model with more cores and made with a better manufacturing process.

      It's beyond BS when you take a chip already in use in servers, cherry pick one that has the best (almost miracle perfect) overclock capability and use what was basically a refrigerator to cool the water cooling system and hype it as a DEMO for some upcoming product. Tis vaporware to compete on paper with a soon-to-be shipping AMD product.

    4. Re: And it was a 32 core machine ... by Rockoon · · Score: 2

      Even quad channel memory cant keep up with the demands of 32 x86 cores on most of the things people want 32 cores for. This is due to the design of the x86 caches leaning towards lower latency instead of towards higher bandwidth. GPU's with lots of "cores" of course have the opposite problem, terrible latency.

      --
      "His name was James Damore."
  3. Because Chipzilla would never .... by UnknownSoldier · · Score: 5, Informative

    /sarcasm Chipzilla would never resort to benchmarking shenanigans ... Oh wait.

  4. Re:And cooled to -10C by Anonymous Coward · · Score: 5, Funny

    No need to cite anything - one of Intel's engineers involved with the demo admitted as much already.

  5. Re:And cooled to -10C by fahrbot-bot · · Score: 2

    Even then it is doubtful it can run at 5 ghz. It also is skylake technology and a 2 year old server chip. My citation is here.

    Wouldn't be the first time someone got suckered by a modified demo. My citation is here.

    --
    It must have been something you assimilated. . . .
  6. Updated: Intel's YEARS of insufficient management by Futurepower(R) · · Score: 5, Interesting

    I've updated this from a comment I made before. To me, it seems like a more in-depth understanding of Intel's management in the past 15 years.

    Intel's insufficient management: Intel has had many years of insufficient management, in my opinion. (Jan. 22, 2018)

    Here is a comment of mine posted exactly 12 years ago: Lower prices are not the answer. Proposal. (June 9, 2006)

    Intel's poor marketing: It is not difficult to find other evidence of insufficient management at Intel. Since the beginning of this year I've gotten 40 poorly considered, poorly written marketing emails from Intel. Whoever writes those ads seems to have almost no technical knowledge and no ability with sophisticated communication. This is an amazingly foolish sentence from emails I got from Intel on March 6 and March 8, 2018: "Up your marketing game with segment-focused campaigns..."

    Recent background: Meltdown and Spectre: 'worst ever' CPU bugs affect virtually all computers (Jan 4, 2018) "Meltdown is currently thought to primarily affect Intel processors manufactured since 1995, excluding the company's Itanium server chips and Atom processors before 2013."

    Linus Torvalds Calls Intel Patches 'Complete and Utter Garbage'. (Jan. 22, 2018)

    Two previous errors in design of Intel processors: Pentium FDIV bug (1994) and the Pentium F00F bug (1997)

    More EXTREME evidence of insufficient management at Intel: Intel was aware of the chip vulnerability when its CEO sold off $24 million in company stock. (Jan. 3, 2018)

    Will Intel be allowed to PROFIT from many years of producing processors with vulnerabilities? Will Intel be treated like U.S. banks in 2008, when many banks profited and many finance system managers got bonuses after the financial crash?

    If vulnerabilities are profitable, would Intel deliberately allow vulnerabilities in its products? Were the previous vulnerabilities deliberate? Did the CEO know about the vulnerabilities previously? Do others at Intel profit from the vulnerabilities?

  7. Re:Updated: Intel's YEARS of insufficient manageme by MrL0G1C · · Score: 2

    This would explain why they're going through bankruptcy proceedings. ~

    --
    Waterfox - a Firefox fork with legacy extension support, security updates and better privacy by default.
  8. Halfassed SPARC by nbvb · · Score: 5, Insightful

    So, Intel demos a halfassed SPARC chip.

    Even freakinâ(TM) Oracle can ship a 32-core, 5GHz monster of a chip ...

    Intel needs a gigantic cooler for a one-shot demo of a chip with less cores and no DAX accelerators.

    My how the mighty have fallen.

    1. Re:Halfassed SPARC by TeknoHog · · Score: 2

      Even freakinÃ(TM) Oracle can ship a 32-core, 5GHz monster of a chip ...

      Yeah, but does it support Meltdown like Intel?

      It might. Depends on the cooling setup.

      --
      Escher was the first MC and Giger invented the HR department.
  9. Re: Not a chance this works by Bing+Tsher+E · · Score: 2

    Intel doesn't care much. The 'opponent' AMD may produce a fine product, but not in a significant enough market segment for Intel to bother caring about. I am not some big Intel fan saying this, just a disinterested observer (the first x86 processor that I can remember noticing I was running that was an AMD part was an 8088 chip).

    AMD/Intel fanboys in threads like this are like dogs in the street chasing motorcycles. Get a clue, just get on an Intel or AMD bike and go for a ride. It's much more fun than huffing tailpipe fumes.

  10. Re:I love an underdog... by Anonymous Coward · · Score: 4, Funny

    What a fun and relevant anecdote!

  11. Hashtag No Shit by Chas · · Score: 2

    Is AMD REALLY causing you to fill your drawers that badly?

    --


    Chas - The one, the only.
    THANK GOD!!!
  12. Re:Very imperfect management, huge worldwide deman by Rockoon · · Score: 2

    Intel isnt making any of the current "compute performance" chips. Thats companies like Google contracting out to companies like TSMC to produce custom chips like the Tensor Processing Unit.

    The big joke is that TPU's are coming off old 28nm fabs. Intel has been closing these while TSMC/etc are still making some big bucks on them.

    Intels key problem is their vertical business structure. The rent-a-fabs are winning. Intels dirty business practices that forced AMD so spin off their fabs into a rent-a-fab that will be first to 7nm is pure fucking gold comedy. Intel is right fucked until it breaks itself up.

    --
    "His name was James Damore."