Slashdot Mirror
Japan's Fujitsu and RIKEN Have Dropped the SPARC Processor in Favor of an ARM Design Chip Scaled Up For Supercomputer Performance (ieee.org)
Japan's computer giant Fujitsu and RIKEN, the country's largest research institute, have begun field-testing a prototype CPU for a next-generation supercomputer they believe will take the country back to the leading position in global rankings of supercomputer might. From a report: The next-generation machine, dubbed the Post-K supercomputer, follows the two collaborators' development of the 8 petaflops K supercomputer that commenced operations for RIKEN in 2012, and which has since been upgraded to 11 petaflops in application processing speed. Now the aim is to "create the world's highest performing supercomputer," with "up to one hundred times the application execution performance of the K computer," Fujitsu declared in a press release on 21 June. The plan is to install the souped-up machine at the government-affiliated RIKEN around 2021. If the partners achieve those execution speeds, that would place the Post-K machine in exascale territory (one exaflops being a billion billion floating point operations a second). To do this, they have replaced the SPARC64 VIIIfx CPU powering the K computer with the Arm8A-SVE (Scalable Vector Extension) 512-bit architecture that's been enhanced for supercomputer use, and which both Fujitsu and RIKEN had a hand in developing. The new design runs on CPUs with 48 cores plus 2 assistant cores for the computational nodes, and with 48 cores plus 4 assistant cores for the I/O and computational nodes. The system structure uses 1 CPU per node, and 384 nodes make up one rack.
"anybody who actually knows what RISC actually means would tell you that any and all SIMD units violate RISC's principles."
No, SIMD units do not "violate RISC's principles" and your saying so only demonstrates your own shallow understanding of what these principles are. RISC may mean "reduced instruction set computing" but that doesn't mean the end game is the smallest instruction set.
RISC is about making an architecture that is easy to implement by eliminating instructions that aren't needed for good performance. In doing this, designers can spend their gates on performance wins rather than on logic that can just as easily be reproduced in software. RISC is about putting gates where they count and not wasting them where they don't.
When you view RISC by it's actual principles, and not just by what the letters stand for, it's quite easy to see how SIMD units are entirely compatible. Of course, RISC as a differentiator has been obsolete for decades now and only exists as a point of argument for people who don't understand. RISC was an interesting topic...in 1988. You're 30 years behind.