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ARM's Own Employees Complain About Anti-RISCV Website (theregister.co.uk)
lkcl writes: Phoronix and The Register have an insightful look into an effort by ARM that is reminiscent of Microsoft's "Get The Facts" campaign. RISC-V's design is a revamp of the RISC concept that is intended from the ground up to fix the mistakes and learn from the lessons of the past 30 years. Power efficiency is 40% better than ARM or Intel. Compressed instructions reduce I-cache misses by 20-25%, which is roughly comparable to the same performance that would be achieved by doubling the Instruction Cache size. Yet despite El Reg's insightful analysis,
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.
Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.
Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.
I don't think I've ever read a more confusing summary.
It might have helped if the first part of this had appeared on Slashdot. But yes, the summary, particular the title, is hopeless. A better title might be: "ARM beclowns itself with FUD against RISC-V"
This is about ARM FUD against RISC-V that appeared yesterday on a new site setup by ARM marketing creeps. It was a shock to people that respect ARM, so much so that some argued it was a hoax. It took some investigation into the FUD site and its origins to convince people.
The fact is that what ARM sells is being commoditized. It's being commoditized because what they sell isn't all that novel any longer. The core of an ARM based integrated circuit is a small fraction of the value of these devices today; they real value is in the peripherals.
Maw! Fire up the karma burner!
I have been reliably informed by slashdot that architectural differences don't matter at all because of something called a translation layer.
For modern, high performance cores like the latest x86's you may be right. With their billions of transistors, large multi-layer caches, out-of-order execution, pulling instructions apart into u-ops (and/or multitude of other tricks employed under the hood), some extra complexity in instruction decoding could be a minor part of the transistor budget. Changing little in terms of raw performance, power efficiency etc and making the CISC vs. RISC debate a moot point.
But that's not what RISC-V is about. It's a clean-slate architecture.
It's meant to scale. For a big high performance x86 a complex instruction set may not matter much, but if you're scaling down into low-power / low cost / embedded cpu's, a simpler ISA means smaller, cheaper, more power efficient devices. For scaling up, RISC-V provides for modular extensions to the instruction set. Making applications easy to move from low-end to higher-end parts (and vice versa). Or if you're into some many-core design, having a smaller / simpler core to start with, means you can put more of them on your slab of silicon.
If virtualization is your thing, RISC-V architecture is designed from the start with that in mind. Not bolted onto a 20~30 year old architecture.
Not to mention there's no IP royalties due should you want to bake your own IC's. For large-volume / thin-margin items, that could be a biggie even if you're talking a few $cents a pop (or thereabouts).
Surely the above isn't all - check the RISC-V website if you haven't already. Given the number of organizations & companies behind, I think it's set to take over a large share in several markets. Probably in the long term though, from the low end up.
It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.
The complexity of the RVC decoder and the complexity of an x86-64 decoder are nowhere near the same.
The x86-64 can have instructions from anywhere from 1 to 15 bytes long, and it takes a lot of processing to determine how long an instruction is, especially with all the prefixes (like the REX prefix that sees so much use in 64 bit code for x86). This necessitates a state machine of some sort to parse the prefixes and apply their modification to the effect of the instruction in question. Each instruction is highly encoded, which requires a complex decoder to determine the length and operands, before the actual performance optimizations like register renaming begin. Additionally, each variable-length instruction may be split into multiple micro-ops. Intel makes highly performant processors despite, not because of, the instruction set.
Unless you have non-standard extensions, RISC-V instructions can either be 2 or 4 bytes (the 2 byte ones being the compressed instruction set). Instructions must be 2-byte aligned. It is trivial to calculate the length of any instruction in such a chip - if the least significant 2 bits are 11, it's a 4 byte instruction, otherwise it's a 2 byte instruction. In 4 byte instructions, the source and destination registers, and the highest bit of the signed immedate are always stored in the same place in the instruction word, allowing register renaming to execute in parallel, to a large extent, with actually decoding the opcode. The 2 byte instructions are not quite as clean, but still much simpler to decode than x86. (See page 70 of the RISC-V user-level ISA documentation.) Additionally, it seems that every 2 byte instruction is equivalent to executing a certain 4 byte instruction. (p. 81)
And yet, apparently RISC-V compressed is more concise than most variable-length encodings. (Including x86-64, IIRC. So much for "x86-64 uses memory bandwidth and cache more efficiently.")
Source for the RISC-V compressed instruction formats starts at page 67.