ARM's Own Employees Complain About Anti-RISCV Website (theregister.co.uk)

lkcl writes: Phoronix and The Register have an insightful look into an effort by ARM that is reminiscent of Microsoft's "Get The Facts" campaign. RISC-V's design is a revamp of the RISC concept that is intended from the ground up to fix the mistakes and learn from the lessons of the past 30 years. Power efficiency is 40% better than ARM or Intel. Compressed instructions reduce I-cache misses by 20-25%, which is roughly comparable to the same performance that would be achieved by doubling the Instruction Cache size. Yet despite El Reg's insightful analysis,
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.

Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.

Comments

Intel

[Anonymous Coward]

ARM is a technology company that makes all of it's money licensing it's IP. If people don't use ARM chips, they don't make money.

Intel is a chip manufacturing company. They have their own CPUs, but they have also manufactured ARM CPUs (XScale) and licensed their IP for other chip manufacturers to use. I don't think Intel particularly cares what CPUs they make, as long as they make money.

So, in the grand scheme of things, Intel probably wouldn't care about making RISC-V CPUs if they could make money doing so, whereas RISC-V is a direct threat to ARM's business model.

Re:Intel

[Logger]

I call hogwash on the claim that RISC-V is significantly more power efficient than ARM or Intel. I could not find the summary's claim of "Power efficiency is 40% better than ARM or Intel. " anywhere in the referenced material.

I'm guessing he's misquoting this line "instruction cache access alone dissipated 40% of the energy in a five-stage RISC pipeline."
Unless someone has come up with a RISC-V implementation that completely eliminates 100% of i-cache access power, in no way can you interpret that to mean RISC-V is 40% more power efficient than ARM or Intel. The paper does claim "[RISC- V compressed programs] fetch 25% fewer instruction bits than RISC- V programs", but that's comparing 2 different RISC-V ISAs; not RISC-V to ARM or Intel.

I don't know enough about RISC-V to really say if it's ISA is inherently more or less power efficient than ARM or Intel. I'd be surprised if it wasn't better than Intel, and there's certainly room for improvement over ARM, but the only way to be that much better is *magic*.

The real reason ARM is scared of RISC-V isn't some theoretical efficiency advantage that has never been proven out, but the free licensing structure. There's a lot of IOT designs out there that just need a good enough processor. There's also high volume embedded processor applications whose roadmaps don't don't foresee the need for continual processor improvements, so they'd rather not keep paying per CPU royalties to ARM when they don't care about future enhancements. In those markets cost is king, and it's hard to compete with free.

Interestingly, the embedded markets I'm talking about don't use JIT. JIT based solutions require more memory, aka more cost. JIT based systems also have longer boot times, which is undesirable in these applications. Think, storage controller.

The biggest JIT ARM users are actually in the smartphone space, and near term that space has other sticky reasons to stay with ARM. Compiler support ( really only the apps are JIT, everything else is C), debuggers, and lot's of other ARM IP that is bundled with the ARM license. That other ARM IP is not something most people outside of SoC ASIC design are familiar with. So giving up ARM is to give up a whole lot more than just the ARM processor, and isn't so easily replaced.

I could imagine China encouraging Chinese companies to build a complete ecosystem around RISC-V, that could compete in the smartphone space though. That would align well with China's strategic goals, and probably scares the bejesus out of ARM. And if that is beginning to happen, I don't see how ARM could actually stop it. Really, they only can try to delay it.

This summary is a mess

[wonkey_monkey]

I don't think I've ever read a more confusing summary. Clarifying that RISC-V isn't ARM's baby would have been a start. The subject of each sentence is also hard to decipher - is The Register's (do we have to call it "El Reg"? That's so twee) analysis about RISC-V, or about ARM's anti-RISC-V site? And so on.

Re:This summary is a mess

[Tailhook]

I don't think I've ever read a more confusing summary.

It might have helped if the first part of this had appeared on Slashdot. But yes, the summary, particular the title, is hopeless. A better title might be: "ARM beclowns itself with FUD against RISC-V"

This is about ARM FUD against RISC-V that appeared yesterday on a new site setup by ARM marketing creeps. It was a shock to people that respect ARM, so much so that some argued it was a hoax. It took some investigation into the FUD site and its origins to convince people.

The fact is that what ARM sells is being commoditized. It's being commoditized because what they sell isn't all that novel any longer. The core of an ARM based integrated circuit is a small fraction of the value of these devices today; they real value is in the peripherals.

Re:Of course they are rattled

[alvinrod]

I wouldn't say that. Companies like NVidia are doing a lot of work in designing cores that are made for deep learning and other types of specialty workflows where a general purpose CPU isn't as efficient or the amount of processing power needed is massive. Others like AMD have developed new interconnect technologies (they call it Infinity Fabric) that can be used to connect multiple small dies together on an interposer. This has massive ramifications as it means you can create massive dies in a much more cost-effective manner. We've also seen both Intel and AMD making moves towards APUs and with HBM (high bandwidth memory) it's eventually going to hit a point where x86 processors can become a SoC to that point that PCs become much more simplified. Maybe this doesn't have the wow-factor of some flashy new invention, but steady progress is often far more important than most of what people want to call "true" innovation.

RISC-V is also an ISA (instruction set architecture) which is not an actual chip implementation. It's very similar to ARM in that it allows for companies to develop their own implementations of the chip, much like how Apple, Samsung, NVidia, and Qualcomm all make their own cores. The only difference is that RISC-V doesn't cost anything to license. You'll still need to pay chip designers to create an implementation if you don't have an open implementation that's free to use and there's no guarantee that any free implementation fits the use case that you'd want to target. Even if it does, there's still no guarantee that someone's proprietary implementation doesn't have such significantly better performance that it's better just to pay the additional cost anyway.

My Thoughts

[DaMattster]

ARM is scared of losing it's death grip over IoT and smartphones. Usually active FUD campaigns bely this real concern. One day ARM will have to come to grips with the fact that it will be toppled. ARM is about to repeat the same expensive mistakes that Microsoft did with its Get The Facts campaign.

Re:I wonder why anyone cares at all

[Alwin Henseler]

I have been reliably informed by slashdot that architectural differences don't matter at all because of something called a translation layer.

For modern, high performance cores like the latest x86's you may be right. With their billions of transistors, large multi-layer caches, out-of-order execution, pulling instructions apart into u-ops (and/or multitude of other tricks employed under the hood), some extra complexity in instruction decoding could be a minor part of the transistor budget. Changing little in terms of raw performance, power efficiency etc and making the CISC vs. RISC debate a moot point.

But that's not what RISC-V is about. It's a clean-slate architecture.

It's meant to scale. For a big high performance x86 a complex instruction set may not matter much, but if you're scaling down into low-power / low cost / embedded cpu's, a simpler ISA means smaller, cheaper, more power efficient devices. For scaling up, RISC-V provides for modular extensions to the instruction set. Making applications easy to move from low-end to higher-end parts (and vice versa). Or if you're into some many-core design, having a smaller / simpler core to start with, means you can put more of them on your slab of silicon.

If virtualization is your thing, RISC-V architecture is designed from the start with that in mind. Not bolted onto a 20~30 year old architecture.

Not to mention there's no IP royalties due should you want to bake your own IC's. For large-volume / thin-margin items, that could be a biggie even if you're talking a few $cents a pop (or thereabouts).

Surely the above isn't all - check the RISC-V website if you haven't already. Given the number of organizations & companies behind, I think it's set to take over a large share in several markets. Probably in the long term though, from the low end up.

Re:I wonder why anyone cares at all

[Anonymous Coward]

It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.

The complexity of the RVC decoder and the complexity of an x86-64 decoder are nowhere near the same.

The x86-64 can have instructions from anywhere from 1 to 15 bytes long, and it takes a lot of processing to determine how long an instruction is, especially with all the prefixes (like the REX prefix that sees so much use in 64 bit code for x86). This necessitates a state machine of some sort to parse the prefixes and apply their modification to the effect of the instruction in question. Each instruction is highly encoded, which requires a complex decoder to determine the length and operands, before the actual performance optimizations like register renaming begin. Additionally, each variable-length instruction may be split into multiple micro-ops. Intel makes highly performant processors despite, not because of, the instruction set.

Unless you have non-standard extensions, RISC-V instructions can either be 2 or 4 bytes (the 2 byte ones being the compressed instruction set). Instructions must be 2-byte aligned. It is trivial to calculate the length of any instruction in such a chip - if the least significant 2 bits are 11, it's a 4 byte instruction, otherwise it's a 2 byte instruction. In 4 byte instructions, the source and destination registers, and the highest bit of the signed immedate are always stored in the same place in the instruction word, allowing register renaming to execute in parallel, to a large extent, with actually decoding the opcode. The 2 byte instructions are not quite as clean, but still much simpler to decode than x86. (See page 70 of the RISC-V user-level ISA documentation.) Additionally, it seems that every 2 byte instruction is equivalent to executing a certain 4 byte instruction. (p. 81)

And yet, apparently RISC-V compressed is more concise than most variable-length encodings. (Including x86-64, IIRC. So much for "x86-64 uses memory bandwidth and cache more efficiently.")

Source for the RISC-V compressed instruction formats starts at page 67.