Nvidia, Western Digital Turn to Open Source RISC-V Processors (ieee.org)

An anonymous reader quotes IEEE Spectrum: [W]hat's so compelling about RISC-V isn't the technology -- it's the economics. The instruction set is open source. Anyone can download it and design a chip based on the architecture without paying a fee. If you wanted to do that with ARM, you'd have to pay its developer, Arm Holding, a few million dollars for a license. If you wanted to use x86, you're out of luck because Intel licenses its instruction set only to Advanced Micro Devices. For manufacturers, the open-source approach could lower the risks associated with building custom chips.

Already, Nvidia and Western Digital Corp. have decided to use RISC-V in their own internally developed silicon. Western Digital's chief technology officer has said that in 2019 or 2020, the company will unveil a new RISC-V processor for the more than 1 billion cores the storage firm ships each year. Likewise, Nvidia is using RISC-V for a governing microcontroller that it places on the board to manage its massively multicore graphics processors.

Comments

Good tech

[Misagon]

I think the article should say "[W]hat's so compelling about RISC-V isn't just the technology".

The instruction set is modern and tight, made to be easy to pipeline and scale. There are RISC-V chips that rival ARM in performance / watt at the same manufacturing process.
The ISA is modular so engineers could strip out the parts they don't need and get more power savings that way.

But I would not say that it is mature yet. There are important parts, such as the memory consistency model that I have not yet seen set in stone.

Re:Whatever happened to step changes?

[mangastudent]

I thought risc was the way of the future when it first came out, yet Intel dominates with their fairly complex architecture. Why and are the problems solvable?

RISC really shined during a brief period where there was an extreme premium on getting every part of a CPU on a single die, and memory speeds weren't totally out of wack with CPU speeds. That favored its approach of the minimum number of transistors on a chip and using memory a bit more wastefully than older approaches grounded in the days when memory was both slow and very expensive, e.g. during the transition from core to DRAM.

Now, of course, we can put relative to those days an infinite number of transistors on a die, and memory speeds are again out of wack with CPU speeds. We've got plenty of main memory, but cache is still dear. To the point that pretty much any execution micro-optimization that causes your working set to exceed a level of caching ends up running slower. And Intel's IA-32 macro architecture didn't make any fatal mistakes like e.g. the VAX's so that it could be made to run quickly without insane effort.