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RISC-V and Linux Foundations Partner to Promote Open Source CPU (techrepublic.com)
"The Linux Foundation and RISC-V Foundation announced yesterday a joint collaboration project to promote open source development and commercial adoption of the RISC-V instruction set architecture (ISA)," reports TechRepublic:
Though some devices that integrate RISC-V will use real-time operating systems rather than Linux, the use of Linux in development will be instrumental as existing tools are being extended to support the RISC-V ISA when developing software on traditional computers. "This joint collaboration with the Linux Foundation will enable the RISC-V Foundation to offer more robust support and educational tools for the active RISC-V community, and enable operating systems, hardware implementations and development tools to scale faster," said Rick O'Connor, executive director of the RISC-V Foundation, in a press release.
In many ways, RISC-V is a hardware equivalent to the open source principles that guide the Linux project, as the ISA is open source, is not subject to patent encumbrances, and is available under the BSD license. [L]icensing fees for Arm or MIPS ISAs -- both of which are fundamentally RISC in principle -- can be avoided by using RISC-V.... As alternatives like Alpha, SuperH, MIPS, and even Intel's own Itanium processors have fallen by the wayside, organizations using those ISAs in their products have had difficult adjustment periods transitioning away, while patent encumbrances largely prevent third parties from continuing development or providing drop-in replacements for those technologies. RISC-V's open nature prevents these issues, as it is possible for any organization to extend or customize their own implementation, and any organization can produce their own RISC-V processors.
Manufacturers like how RISC-V CPUs aren't restricted to a single manufacturer, according to the article, which points out that NVIDIA and Western Digital have both announced plans to use RISC-V in some upcoming products.
RISC-V is also "gaining popularity in Internet of Things, low-power, and embedded applications," and Western Digital even plans to ultimately transition its annual consumption of processors -- one billion cores per yer -- to RISC-V.
In many ways, RISC-V is a hardware equivalent to the open source principles that guide the Linux project, as the ISA is open source, is not subject to patent encumbrances, and is available under the BSD license. [L]icensing fees for Arm or MIPS ISAs -- both of which are fundamentally RISC in principle -- can be avoided by using RISC-V.... As alternatives like Alpha, SuperH, MIPS, and even Intel's own Itanium processors have fallen by the wayside, organizations using those ISAs in their products have had difficult adjustment periods transitioning away, while patent encumbrances largely prevent third parties from continuing development or providing drop-in replacements for those technologies. RISC-V's open nature prevents these issues, as it is possible for any organization to extend or customize their own implementation, and any organization can produce their own RISC-V processors.
Manufacturers like how RISC-V CPUs aren't restricted to a single manufacturer, according to the article, which points out that NVIDIA and Western Digital have both announced plans to use RISC-V in some upcoming products.
RISC-V is also "gaining popularity in Internet of Things, low-power, and embedded applications," and Western Digital even plans to ultimately transition its annual consumption of processors -- one billion cores per yer -- to RISC-V.
TSMC will fab them for you.
Western Digital plans to use RISC-V processors in their storage products starting next year. Most likely they will be fabbed by TSMC.
It is not clear if these RISC-V chips will be available to other companies or to the general public.
These chips are available to anyone who wants a fab to make them
It is not that simple. You can't just take a pile of Verilog source, even code that runs fine on an FPGA, and slap it onto real silicon. There is a huge amount of work fitting the design to the process. Of course, you could just make a metalized gate array, but that will give you little advantage over just sticking with a core on an FPGA.
there's no secret sauce there.
Actually, going from a raw design to a working state of the art chip involves plenty of "secret sauce".
Unfortunately, many of those patents for performance enhancing features using out-of-order execution were based on a single research paper. That was implemented in one CPU vendor design, then cross-patented to other CPU vendors. RISC-V has the advantage that it doesn't have those vulnerabilities baked in and built upon.
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Low-end boards are not that expensive. The HiFive1 are just 59 $ in single-unit quantitities. Philipp
That would be insane - an SSD disk drive with a built in GPU / compute engine.
RISC-V does not have an integrated GPU, nor does it even have SIMD vector instructions. Things may change in the future, but for now it is in no way a "compute engine".
It is ideal for low power embedded systems ... like drive controllers.
Yes, it is very clear.
No, they will not be available to other companies, or to the general public.
This article, about the Linux Foundation partnering with RISC-V to encourage creation of chips available to the general public. Western Digital was mentioned because they're an example of what is being done already.
If those things were the same, they would not have even mentioned them both.
an SSD drive mostly only needs a fancy multiplexer. The computational part could be done on a SOT-26 package micro otherwise.
That's why the economics lean so heavily on them doing it themselves; what they need is about the cheapest possible embedded processor with that pin count. Not having to license a design means they push the costs down to the theoretical minimum.
If you have the Verilog and a working FPGA, a standard cell ASIC is pretty straightforward, assuming that good design practice was used for the source. For a given level of performance and a given process node, standard cell will have better timing margins.
AMI used to offer FPGA to standard cell conversion as a service.
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