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MIPS Goes Open Source (eetimes.com)
Junko Yoshida, writing for EETimes: Without question, 2018 was the year RISC-V genuinely began to build momentum among chip architects hungry for open-source instruction sets. That was then. By 2019, RISC-V won't be the only game in town. Wave Computing (Campbell, Calif.) announced Monday (Dec. 17) that it is putting MIPS on open source, with MIPS Instruction Set Architecture (ISA) and MIPS' latest core R6 available in the first quarter of 2019. Art Swift, hired by Wave this month as president of its MIPS licensing business, described the move as critical to accelerate the adoption of MIPS in an ecosystem.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
You're missing the big picture here. While SPARC and MIPS lost out to x86 they are both mature ISAs with many competing features to x86. For example they have their own SIMD implementations on the FPU. This will be a big boon to RISCV. One of the places where RISCV will find it hard to compete with x86 and ARM is that they both have some very important patented extensions. Intel beat its competitors not because x86 was technically better, but because they were able to catch the widespread consumer adoption in PCs which lead to them being able to outspend others in process node technology. Now that TSMC has caught up to them a great deal, the only other major performance hurdle are the ISA extensions and optimizations. If MIPS is truly FOSS then many of those mature features can be re-implemented into RISCV and earn a massive performance boost. Specifically the SIMD extensions and VPE (MIPS equivalent to hyper-threading) will be useful.