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New Merced Patents
Intel and HP have been awarded
2 patents which reveal more about Merced. Speculatively
executing both code paths originating at a conditional branch
wastes resources which could be better used concentrating on
one path. By applying speculative execution only when branch-prediction
will probably fail, speculative execution is minimised
to the cases where it will really help. In pretty much unrelated
news,
Intel's selling toys which might actually teach kids something.
Apparently, Intel still doesn't know how to design a microprocessor. The design of IA-64 ought to be nothing more than a super-fast RISC core with the legacy IA-32 instruction set emulated in microcode. But apparently they're still wasting silicon on such silly crap as speculative execution and branch prediction. Duh.
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Are they EVER going to ship IA-64??
Geez, it's just getting stupid. I wonder whether they're going to ship it first as a server-only type chip... (like they did with XEON)
Looks like they're going to spend so much time trying to do a decent job of emulating the x86 instructions that it's going to hamper the development of the rest of the chip.
Christ, if they just made a chip that was fast enough to do it they could just emulate x86 in software.... I'm sure it could do it now. At least then nothing would hold back future development
Whatever... i'm sticking with PowerPC.
[Cough!]
... we're going to need a bigger wall ...
Methinks IA-64 is VLIW deep down
Yawn...Waiting for McKinley...HP at least have a clue about real processor design...
While we wait...Alpha or UltraSparc anyone?
Come the revolution
What are you basing this on? Modern architectures have to have very deep pipelines (I think that the K7 will have 7) in order to maintain competitive speed. If it weren't for speculative execution, the processor would have to stall its pipeline every time a jump instruction was encountered. This is a rather serious performance hit, which would occur quite frequently in practice. I've never designed a processor myself, but according to all that I've read, neglecting speculative execution in this day and age is a rather Bad Idea.
Also: for what it's worth, the IA-64 is supposed to be a VLIW processor (or, as Intel calls it, EPIC), not a RISC design. These are more philosophies than set guidelines, however, so the matter is somewhat open to interpretation.
--Lenny
Is that really necessary?
Hmm,
;^)
Almost all processors of the current generation have branch prediction (Alpha, HP, PowerPC, MIPS).
Many processors also have speculative execution.
Very few processors have microcode for most instructions.
Apparently nobody (but you) knows how to design a microprocessor
And yes, I have designed a microprocessor. Duh.
...just like many other vendors of CPU for general-purpose computers. It's not as if Intel are the only folks on the planet doing speculative execution and branch prediction, which I guess means that, by your lights, the other vendors doing that don't know how to design microprocessors, either. Sic transit gloriaDigital^H^H^H^H^H^H^HCompaq, Sun, MIPS/SGI, HP, etc.
Perhaps they're all going in the wrong direction, but thumping only Intel for doing, say, branch prediction is an error, given that the folks I cited did it as well....
Are these comments YOUR comments, or are you quoting? If quoting, you need an attribution (or at the very least quotes/italics.
As opposed to on the surface, where it's something else?
and 10/10 agree that GNOME sucks worse?
From what I recall, "buckets" (which contain three instructions apiece) are 128 bits wide. If opcodes are 41 bits wide, I wonder what the other 5 bits are used for, and how.... (128 - (41*3)) == 5.
As for the branch predictor, it sounds somewhat interesting. The new part is the "predict that predictor is wrong." chuckle Talk about second-guessing...
The driblets about predication scheme sound bizarre, but then I'm probably tainted by the TMS320C6000-way of doing things...
Program Intellivision!
This is ironic when you consider how much static prediction Merced relies on compilers to perform.
Program Intellivision!
But the Power PC is still only a little faster than the Pentium family!
Have you ever taken a class in computer architecture? No of course not...if you had you wouldn't be spouting off at the mouth....
In a piplined processor, branch prediction increases throuput by GIGANTIC amounts.
-harry
heymann@andrew.cmu.edu
Actually I'd assume the instructions would be 32 bits long - it's a nice number, and they probably don't even plan on using all 4 billion instructions (always good to leave room for advancement). There was an article referenced directly or indirectly here (slashdot) a few days ago that had the IA64 architecture explained. The packets will contain extra bits that will be used for some kind of flagging system if i remember right. They'll be used after multiple branch execution to determine which branch is the failed one, and thus which one to "cut".
Quick, someone patent a method whereby you predict when the prediction of branch prediction will fail, and thereby do speculative execution anyway!
Yea ok I'll believe it when I see it. As it is we know that Intel can take a RISC and make it work on CISC instructions. Then they can ramp up the speed so it outruns the superior Power PC. Don't bet against Intel yet.
Besides I can't use the AlteVic technology because you cannot get G3 motherboards. I would have to buy an Apple to do it.
Ummm
Isn't that description of a "super-fast RISC core with legacy IA-32 instructions set emulated in microcode" something similar to a Dec Alpha 21264 running at 500MHz and FX!32 or something?
Maybe its just 'or something'...
I do like Dec Alpha's style however, so I won't criticize you on that, but it isn't a waste to do spec-execution and branch pred, if it can get a greater than 50% success ratio... It really does speed up the CPU if a guess is correct.
Nice to see Intel get bogged by delays and screwups, however, as it gives AMD, PowerPC, and Digital Alpha room to shove and fight...
-Like my nick?
Anonymous Shepherd
-AS
*Pikachu*
Damn... clicked on the wrong button at the end of that comment....
That last line should read...
...MacOS X Server/LinuxPPC versus PC-based Linux and MacOS X/MacOS 8.x versus Windows 98/NT perspective.
This has already been implemented in HP's PA-8500 processor and improves the accuracy of branch pridiction. If you visit the HP site and search around for the PA-8500 architecture description they've got a great writeup on it.
As for the branch predictor, it sounds somewhat interesting. The new part is the "predict that predictor is wrong." chuckle Talk about second-guessing...
It's already been implemented in HP's PA-8500 which gets SpecInt95=32 and SpecFp95=54 at 440MHz. For a description of this feature of the PA-8500 architecture, surf on over to the HP site at http://www.hp.com and search on PA-8500. At least one document specifies how much this feature helps in improving branch prediction. I can't remember the numbers, but I do recall it was significant.
How can they patent it? the PowerPC has it since the 604
-Kz-