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E2K Press Conference 2/25/99: Linux Kernel 2.0 boots
Yuri Kiryanov writes
"Elbrus, the maker of the E2K processor, has released
details from their
recent Press Conference.
The highlights are that they have a Native Linux Kernel 2.0.34
running on a multilevel simulation model (including Verilog
level RTL). Their native compiler achieves 8.5 FPU instructions
per cycle. The E2K has SMP Built-in, should have Merced compatibility and only loses 20-30% speed
when compiling foreign instruction sets with respect to the
E2K's native performance." Note: the site is pretty slow
so be patient. It's now
in English and will soon post more E2K info.
All this is very well, but what is their plan to build the thing?
Had to try.
Unless you own intel stock (or stock from one of the other processor companies), these Elbrus announcements can only be construed as good news. If they are true, then the competition in the market place will have increased--which will ultimately lead to better products for the consumer. If this processor remains vaporware, then there is no overall loss.
www.elbrus.ru was down within minutes of the announcement. Might it be possible for /. to cache some of the articles before posting their addresses? BEFORE they get /.'ed?
Elbrus International made som decent webpages.
it is slow to download your WWW pages, if you maybe have the option, put up some mirrors in Europe, Asia, US, Mediteranian area and Africa?
Cool, heh heh, we could take, like 16 multilevel simulators, and, like network them, and run beowulf, huh?
2.0.x does indeed have SMP support, although rather primitive. It is essentially a spin-lock around the entire kernel. I.e. only one CPU can run in kernel mode at a time. This means that programs that spend much time in the kernel (I/O, file access, etc) don't see much improvement on an SMP box running 2.0.x. On the other hand, programs doing stuff in user space (rendering, tracing, mandelbrot, cracking rc5) run faster.
The extra stuff in 2.2.x wrt to SMP is that instead of a single lock around the kernel, the access is a lot more fine-grained (i.e. locks around smaller portions of the kernel).
2.0.x series of kernel does do SMP. 2.2 just does it better (finer grained kernel locks, among other things).
:)
This E2K things just SMELLS fishy. I say, "Don't believe the hype." Remember WEB compression? They can promise all they want; I'll only care when they deliver (of course, I not an investor who needs to be impressed
PRESS-CONFERENCE QUESTIONS AND
ANSWERS
Q: Has IEEE754 standard been implemented in floating point units?
A: Implemented in full, including the non-normalized numbers.
Q: What is the maximum number of floating point operations that can be run
in one clock?
A: In each clock 8.5 floating point operations maximum can start (the division
operation can start once in two clocks, the rest operations can start in each
clock).
Q: Are the L1 and L2 caches non-blocking, if "yes", how many misses may
occur?
A: Both caches are non-blocking and allow over 32 misses (Certainly, if the
pipeline does not stop earlier due to that any operation may require the LOAD
operation result).
Q: As is known, ALPHA 21264 abandoned the use of the structure that had
been implemented in 21164 - a small but two-clock L1 cache and
comparatively big but multiclock L2 on chip cache. Why do you use this
structure?
A: We modelled 2 versions of the on chip cache structure. The first one: 3
clock 64 KB cache, the second - 2 clock 8KB L1 cache and 8 clock 256 KB L2
cache. The modeling results have shown that the 2nd version gives better
results on our code. It should be noted, if the technology allows, we will
increase the size of L1 cache leaving the delay time of 2 clocks.
Q: What simulators did you use to specify the characteristics of your
microprocessor?
A: We have a multi-level simulation system. All simulators are consistent.
The most precise and consequently the slowest is Verilog RTL model. It
operates with the speed of several wide instructions a second, that is why it can
be used only for small engineering tests. The next level is a clock precise
simulator of the microprocessor, which allows on suffiently big tasks (SPEC
benchmarks) to precisely estimate the microprocessor performance. All
memory levels (cache and main memory) are simulated in it, as well as all
hardware Interlocks (i.e. all phases of the hardware pipeline). The fastest is
ISET simulator. It runs with the speed of 2 mln. wide instructions a second and
makes it possible to execute practically any user's applications.
Q: Will you be able to do a symmetric multiprocessing on your machine?
A: We binary compile the operating systems themselves, Microsoft including,
that is why they will operate in the way how they are written. In our
architecture everything is implemeted such that, if multiprocessing has been
taken into account specifically in OS, then it can be ensured.
Q: Have you already worked with OSs supporting multiprocessing?
A: We have compiled Kernel OS Linux 2.0.34 using Elbrus compiler and
executed on the machine simulator.
Q: Binary compilation really looks like a successful solution to ensure
compatibility with å86. But why do you think your design will be compatible
with IA-64, you know the IA-64 instruction set has not yet been declared in
press.
A: Someone, who has already signed NDA with Intel, apparently knows IA-64
instruction set. We don't. However Merced, as is known, will be compatible
with x86 and will have to be compatible in basic operations and data
presentation with x86. Besides, Merced like our E2k makes use of the explicit
parallelism approach. Since in primitive operations (including memory access
and floating point arithmetics) our processor is x86 compatible, we assured
that after some minor modifications, after IA-64 is declared, our processor
will be IA-64 compatible as well.
Q: Don't you think that the performance losses by 20-30% with the binary
compilation of x86 codes are big, you know many companies, Intel among
them, put greater effort into performance increase by the same 30%?
A: Actually, with the binary compilation as compared with the source code
compilation, it is impossible to restore a portion of information in analysing
the binary code. This is the reason why the losses in the the binary compiled
code performance occur. But remember that these are the losses as compared
with the optimized similar native code of E2k. Since our microprocessor will
be 3-5 times faster than Merced, we will be faster than Merced in the
combined mode even with regard to the losses in binary compilation.
Q: To reach the declared performance a native compiler is needed. The
compiler for such an architecture is sophisticated, what is its reliability level?
A: We have an optimizing compiler for E2K. We use it for compiling
benchmarks and running them on the cycle-precise simulator. Besides our
microprocessor has one more unique feature - secure programming. Using
this feature we can fix sufficiently bigger number of bugs in the programs as
compared to the present-day computers. In particular we have compiled in
this mode SPECint92 and SPECint95 benchmarks and have fixed over 30 bugs
in them. We use this mode to debug the compiler itself. We translate our
compiler in secure mode and then run on simulators. This allows to
sufficiently increase the compiler reliability. The compiler team is highly
skilled, it has been working on such compiler for over 10 years, and the current
compiler version is already the third for this period of time.
Q: But this only is insufficient. How do you test your compiler?
A: We perform regression testing. We compile and run benchmarks, we have
compiled and run OS Linux, we have a 600 MB testing base consisting of
programs in C language. All of them have been compiled and executed on the
simulator
If this is less than vapourware,
let's see them comply with the
GPL and release the source to the
undoubtedly large changes they
made to Linux and GCC.
However, I somehow doubt this is
actually a substantial concept
and not just a plot to get some
gullible VC cash into a dubious
Russian scheme.
Rich.
Think Intel P4.
I am thinking that built in smp means that the processor supports use in smp configurations, like the p2 and unlike amd chips.
~Nik
First off...under the GPL, they must make available their source code (linux, kernel, gcc, and possibly others).
Second off, this is the thing Microsoft gets slammed for all the time, announcing vapourware...
Let's see the goods, E2K folks, put up or shut up.
I can make a software simulation of a 256-bit processor running at a simulated 1.2 terahertz, does us no good though, does it? MAKE the god damn thing, THEN post the public affairs fluff
"Try running NT4 on a 486/66, 16megs RAM, 200meg hard drive for 6 months. I have...*cringe*
Only then will you properly loath it"
Ha! Try running it on a 386/16, 8MB RAM, 60MB fixed disk (SCSI at least =) with 1/8 kbit/sec Internet connection. THEN you will loathe it.
I won't even get into how you run NT4 on a 386SX.
They are not advertising this chip so end-uers will put off their Alpha or Merced purchases...
They are advertising so they can find a partner to produce the chips.
This is not a product announcement as much as a call for a partner.
AMD should buy out this company and start making these chips on the same .18 micron process as the k7 will be. heh. even if it takes them two years to get everything up and running, they would still be light years above intel. speaking of intel, don't they have $7 billion USD in cash somewhere?? do they have something better to drop 1/2 billion on??
cjluthy@engineering.uiowa.edu
Finally, these guys have AFAIK never designed a single chip CPU.. Oh, they've done some really fast systems considering their limitations in process technology, but there are some differences between thousands-of-chips CPUs and single chip ones. Elbrus is not some no name company in Russia. The Elbrus series cpus are used in Russian Super Computers. Not only that Elbrus was the old Soviet Mainframe makers. They've been making chips since the begining of the Soviet Computer revolution. And unlike most CPU makers in Russia they actually designed their own cpus in addition of coping western designs. I don't know about the rest of your comments, but I know for sure about Elbrus history.
...just check their old web site (in Russian :)
Babayan's own daughter work at SUN...ask her - osana@eng.sun.com
Let's not get loose with the word FUD.
FUD stands for Fear Uncertainty and Doubt.
When someoen makes claims that deflates someone else's efforts based on speculation, disinformation, and misinformation it is FUD.
If you need some silly acronym for it call it
HEB: Hyperbole, Exaggeration and Boasting.
Claiming that you have a chip design that is 5 times fater than Merced is not FUD it's HEB.
bperkins@netspace.org
Why is everyone thinking that they used GCC? A skilled CPU design team really wouldn't have to resort to hacking at GNU's code. Even I've written optimizing compilers.
Hewlett Packard did the lion's share of the design for Merced, yet they didn't feel they had the factory space to achieve a profitable economy of scale. Sounds like a pretty familiar story to me.
> I can make a software simulation of a 256-bit
> processor running at a simulated 1.2 terahertz...
Uhh.. Can you?
MAKE the god damn thing, THEN post the
public affairs fluff
Uahhahahaha!!!
... at least they are running Apache..
Apache/1.3.3 Server at www.elbrus.ru Port 80
You don't seem to realize that:
a) It is incredibly expensive to build a fab suitable for cpu production ($ 1 billion+)
b) Such technology is not present in Russia
c) The state of Russian economy (really bad)
Not wanting to spread possibly stupid rumours - some people in comp.arch are suggesting that Elbrus is in some way affiliated with Transmeta and, if you think about it, who would be a good hacker to have around if you're binary-translating the Linux kernel to run on a VLIW CPU (which is what Transmeta's secret project is more or less about, according to rumours - i.e. a VLIW-like CPU with enhancements for efficient emulation of other CPU's instruction sets)? Funny, that.
>Their native compiler achieves 8.5 FPU instructions per cycle
>On what code!? It's elementary on some codes and all but impossible
>on other... This statement in and of itself is only FUDish,
>and damaging if they really have a product.
It is only damaging when people like you dismiss them without reading the announcement. It says:
> In each clock 8.5 floating point operations maximum can start
> (the division operation can start once in two clocks, the rest operations
>can start in each clock).
If you still don't get it, 8.5 cycles is the theoretical maximum, not a measured average on real software. What this yields in actual performance remains to be seen, but the information as such is just what anu cpu maker usually likes to brag about.
I get the impression from both Elbrus and Transmeta that they are source translating Linux, but binary translating NT.
Erik Corry sans cookies
One thing about Russia is they have notoriously bad fabs. One of the things about Russain chips is that they are usually designed better so that the poor output from the fabs won't destroy the chip.
But this chip looks like it does need high quality production facilties. Personally, I think Sun andmaybe IBM are going to make the chips. I think it was mention before that Elbrus sold sun computers in Russia.
I guess they don't really believe in it.
That's likely not the case at all. There are all sorts of business factors which come into play in making these sorts of decisions. Does IBM or Motorola have $1b in cash reserves they can use to finance an experimental chip design? Probably not; while they have cash reserves, they probably already have it earmarked for other projects. Does IBM or Motorola have management that is sufficiently clued to make an informed decision about the E2K processor? 50-50 and pick 'em. Will the E2K be able to use existing American fab plants? Probably, but that's still another chance factor.
Elbrus is actively looking for business partners. The fact that major American companies aren't beating a path to their door has nothing to do with whether or not it's a good idea.
The Amiga was (is) a great computer, and look at how long it languished looking for a buyer.
All of them
If I remember correctly, the earlier Linux kernels did have SMP, it was just horrendously inefficient. I only have one processor though so I wouldn't know. ;)
Daniel
Hurry up and jump on the individualist bandwagon!
Secondly, I very much doubt you'll get anything terribly exciting out of the patches they've applied to Linux -- most of the kernel is really pretty portable these days, the main bits which aren't are all hardware-related, and a lot of these can just be ditched when you're running on a simulator.
Of course, I'm sure a lot of people would like to take a peek at the compiler. Not least Intel and everyone else who's struggling to write a decent compiler for Merced. I suspect they'll be keeping the important parts of that under their hats though, at least for the time being.
1. The reason they can't manufacture it and demo it is because they don't have a fab, and they don't have money to contract with an existing fab. Insisting that they have it in silicon is simply not realistic.
2. They have several Verilog descriptions. One of them is extremely high level, logicly. One is relatively midlevel, and one is RTL, as in Register Transfer Level, I believe. This means they're read to send it to the fab soon.
3. I understand the anger at not being able to see it, but it might not be FUD. This isn't vaporware that no one ever intends to release, this a processor thats been sitting around for years because they can't afford to produce them, and they've had years to work towards the goal of getting it to were it is now, not having 18 months to turn out a product that just barely works, and isn't particularly good, but it works.
Andrew Gardner
Outside of a dog, a book is a man's best friend. Inside a dog, its too dark to read.
Silly Poster!
Don't You know what EPIC is?
(obviously stated to the tune of that famous Trix line, AND I know it's not completely accurate but hell, HAD to say it!)
> I may be wrong here, but I really thought that SMP support for the linux kernel was only available in the 2.1.x and the 2.2.x series of the kernel.
:-) SMP has existed since 1.3.somethingorother, I think. It does exist in 2.0.x, but is implemented in a fairly inefficient way. The 2.1.x/2.2.x SMP is a much better, more scalable implementation.
You are wrong
Eric
I just love how they can bench non-existant cpu's. If Intel and AMD could do this to create FUD about each other, don't you think they would have done it? I personally take everything that doesn't even have a prototype with a brick of salt (because the grain doesn't do the job for this).
i don't know where I was going with that one.
It makes perfect sense. You can have RTL and even transistor level layouts for a great architecture after spending a few million dollars (less if all your employees are Russian), but to manufacture it you need a modern fab, which costs many billions of dollars. Not everyone has access to that kind of capital, and that is no reflection on their skills as designers.
Since when are there export restrictions on CPUs ?
I can make a software simulation of a 256-bit processor running at a simulated 1.2 terahertz, does us no good though, does it? MAKE the god damn thing, THEN post the public affairs fluff.
I'd be amazed if you could. They have an RTL level description of the CPU in Verilog. Thats the lowest level description that can be produced by hand, and specifies the datapaths and the degree of parallelism precisely. This is then fed into a synthesis/place/route flow to produce the GDSII that is sent to the fab. That process in largely automatic, although complex designs like CPUs require some manual intervention, and it can take a few hundred man years (six months or so for a CPU design team) to complete.
You may be able to write a high level C simulation of CPU at 1.2THz, but RTL Verilog is a whole different matter.
Simply, they probably;
a) feel that an established Western brand would give them better brand recognition in most markets;
b) don't have, and due to the parlous state of the Russian economy cannot afford to build, modern fabrication plants of the necessary level of technology (it being a reasonable assumption that we're talking sub 0.25 micron tracks here), in order to produce such a processor themselves.
I feel either or both factors have to be in play here.
Completely true.. Still though, the fact that they've run Linux on it is a bonus for us (us being the Linux geekies out there).. I really would like to see more serious specs on this thing, and if they DO intend to ever build it (or if anyone intends to ever build it) what the plans are for an accompanying chipset? A processor alone doesn't make a system, and if it's all that fast the chipset and memory interface (and perhaps even memory?) to go with it will need to be created too..
Jim
If I'm not back again this time tomorrow...
This stuff actually hurts these guys (if they are serious and not a big hoax). I'll have fun and critisize some of this:
;-)
Their native compiler achieves 8.5 FPU instructions per cycle
On what code!? It's elementary on some codes and all but impossible on other... This statement in and of itself is only FUDish, and damaging if they really have a product.
The E2K has SMP Built-in
And 'built in SMP' means what?? Cache coherence? Two cores in the same chip?
should have Merced compatibility and only loses 20-30% speed when compiling foreign instruction sets with respect to the E2K's native performance.
As very little is actually known about Merced, this is more than a little silly...
And re: the SPEC numbers.. Please DO show me the memory interface for those numbers..
Finally, these guys have AFAIK never designed a single chip CPU.. Oh, they've done some really fast systems considering their limitations in process technology, but there are some differences between thousands-of-chips CPUs and single chip ones..
I'm certain a lot of nice people will correct me where I'm wrong
Again: This kind of publicity could be damaging to them if they really have a product. Lots of people will start to think they're just like me: hot air speakers
Has it ever occurred to you that God might be a committee?
Has it ever occurred to you that God might be a committee?
--- Jubal Harshaw
It's been availible since 1.3.something. SMP is why Linus upped the major version. The misinformation probably comes from the fact that SMP is much better in 2.1/2.2
Has it ever occurred to you that God might be a committee?
Has it ever occurred to you that God might be a committee?
--- Jubal Harshaw
At once as in two cores or at once as in switches on L1 cache miss?
Has it ever occurred to you that God might be a committee?
Has it ever occurred to you that God might be a committee?
--- Jubal Harshaw
The processor has 'backing registers' and keeps one thread 'sleeping' there. When the running thread wants to access data not in L1 cache the CPU does:
1. Starts to fetch data.
2. Switches to other (sleeping) thread.
Ok?
Like TERAs stuff and the latest PowerPC AS.
Has it ever occurred to you that God might be a committee?
Has it ever occurred to you that God might be a committee?
--- Jubal Harshaw
Which single-chip CPUs have they made? All claims I've read have been about multi (100s or 1000s) chip CPUs.
Has it ever occurred to you that God might be a committee?
Has it ever occurred to you that God might be a committee?
--- Jubal Harshaw
When it costs over a $Billion to build a modern fab, don't you figure only the biggest chipmakers can actually afford to run their own?
Q: Have you already worked with OSs supporting multiprocessing?
A: We have compiled Kernel OS Linux 2.0.34 using Elbrus compiler and executed on the machine simulator.
I may be wrong here, but I really thought that SMP support for the linux kernel was only available in the 2.1.x and the 2.2.x series of the kernel. Is it just that they run the non-SMP kernel on an SMP simulation???
"...Beer..."
No, SMP was available in the 2.0.x kernels. It just didn't work nearly as well (could lock up the system/worse performance).
He said, "You'll be able to tell your grandchildren that you helped assemble the first NT supercomputer," and I cringed.
I know you guys are in San Jose and busy, but I've submitted this article twice, once on Saturday, and once on Sunday. What's taken so long for it to be posted?
He said, "You'll be able to tell your grandchildren that you helped assemble the first NT supercomputer," and I cringed.
not to start anything really, but a friend of mine heard that IBM had purchased something from a russian company, like chip wise... as of right now i don't know much more, but that what the buzz was...