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Troubles with Merced

Brandon Bell writes "Everyone has their theory on why Intel's Merced is in trouble. Kraemer just wrote an opinion piece that discusses two problems he thinks its facing: the compiler and the sales model."

10 of 90 comments (clear)

  1. The man is clueless; EPIC = VLIW by Anonymous Coward · · Score: 2

    EPIC means the following:

    1. The compiler has to explicitly package instructions that have no dependences into parallel issue packets. This task is currently
    done by hardware in superscalars.
    This means that you can't just slap another CPU onto the board to make things faster:
    the parallelism is in the instruction level and is compile-time determined; most bindings are done
    statically. For this to work right,
    almost all instruction, pipeline and functional units characteristics have to be exposed. For example, for software pipelining (a technique to
    overlap instructions from different iterations of
    a loop) to work, pipeline latencies, and functional unit resource constraints at each time step has to be carefully considered.

    2. EPIC is basically VLIW, but don't say that because all VLIWs (except DSPs like TI's C6) have been commercial failures. Besides it's not as salesirific as VeeEllEyeDoubleU.

    3. The compiler is crucial. So far, only Univ of Illinois IMPACT group and HP CAR group really really knows how to build one well. (My opinion
    of course)

    4. For more technical info, read comp.arch,
    look at proceedings such as MICRO. See also www.trimaran.org. Just don't listen to the clueless.

    Allen (leunga@cs.nyu.edu)

  2. Very little technical content. by Anonymous Coward · · Score: 3
    The article has very little technical content. And it may not be accurate even.

    I didn't knew that Carnack was the semi-god of compilation research, and I thought that some people had OSes running on Merced simulators.

    The sales model: of course Intel made a gamble ; but the gamble is that you couldn't make much architectural optimization on current RISC (maybe that's why people are throwing away die area with multiple MMX, 3DNow!, whatever "multimedia/SIMD" units), so a new paradigm shift could outperform older units. Basically, Intel is betting that superior performance is a valid reason for being (partly) incompatible with x86 (or to keep up with competitors).

    The a huge part of Merced issue is essentially technical, and the article is just completly out in this respect. Please, someone fix this and post relevant URLs...

  3. Buzzwords make it easy to spot the idiots by Anonymous Coward · · Score: 4
    This guy clearly doesn't know anything more about what EPIC is other than what the acronym expands too.

    Even from the small amount of information published about IA64, it is clear that there is absolutely no support for automatic scaling simply by adding cpus. EPIC refers to the way each individual cpu decodes the instruction stream. EPIC is no more inherently multi-processor than the current IA32 instruction set.

    To get automatic scaling, you need something like Tera's Multi-Threaded Architecture. Too bad they can't seem to ship the damn thing, and that it costs a couple of million.

    See: http://www.tera.com/ for more info.

  4. Time for change? by bjk4 · · Score: 2


    If the trouble is in that the money model does not work with easier to upgrade hardware, then maybe the model needs to change. Currently Dell and Compaq make money selling whole computers. Perhaps they should sell or lease parts in addition to cases. That way you could change the CPU every few months and keep current, for a fee of course.

    Time and progress won't hold still, so perhaps you shouldn't.

    -Ben

  5. It's not just _a_ compiler by bhurt · · Score: 2

    It's not just _a_ compiler that has to be worked over, it's all of them.

    In addition, it's widely accepted that there will be faster RISC CPUs available then Merced when Merced ships, and even faster x86 chips (at running x86 binaries). Before using this to claim that Merced is dead, remember that this was true of the initial RISC chips when they came out. What this means is that it'll simply take a while for EPIC to mature and for the advantages to come to the fore.

    The problem is that Intel doesn't have much of a choice. Well, I suppose they could have gone for a standard RISC chip. But something post-x86 is necessary. If nothing else, the 32-bit limitations of the architecture are hurting Intel's sales in the lucrative server market (where 10's of gigabytes of RAM are common, and 100's not unknown). The desktop user probably won't care for another 4-5 years, but the server market started caring 3 years ago.

    One interesting note in all of this is how this is affecting the Intel/Microsoft relationship. By it's actions, Intel has no confindence in Microsoft being able to ship an Enterprise-ready 64-bit clean OS any time soon. Not that I blame them.

    Intel is learning one nice feature about open-source operating systems- they don't have to depend upon someone else to support their chips. For a small engineering investment, they can do it themselves- and if you want something done right, doing it yourself is a real good idea. Making a small investment in a small company (like, say, Redhat) makes a lot of sense in this context.

    That being said, I think EPIC is an interesting design with a lot of long-term potiential. Standard RISC processors have a hard time averaging more than about 2 parallel instructions. Research done by HP indicates a lot more than that is possible- it's just computationally infeasible for the _processor_ to find it.

  6. Only half right by Doug+Merritt · · Score: 4
    Certainly the compiler is known to be a difficult important issue with Merced, so that part is sort of right -- although I don't see that as a reason for them to slip ship dates.

    But I don't know where he got this idea that Merced automatically makes all applications multi-processor ready; that's just plain wrong. High end processors have had multiple execution units for many years, which allows them a small amount of very fine grain parallelism: on average perhaps two instructions can be executed at once. Sometimes when you're lucky it can be more than two for a short burst. Merced will *not* be able to keep all 7 of their execution units busy 100% of the time, but they may get lucky and do so for an instant every once in a while, if their compilers are really good.

    None of that has anything whatsoever to do with multiple cpu's. The situation with those will be unchanged from the situation today with multiple e.g. Pentiums: applications won't take advantage of more than one cpu unless they are explicitly coded to do so.

    Therefore the conclusion of the article is dead wrong: the business model won't change, because he just misunderstood the issue with parallelism.

    --
    Professional Wild-Eyed Visionary
  7. RISC? Whadda ya mean, "RISC"? by ultra1 · · Score: 2
    "The amount of openly available published research in the RISC compiler community is significant, and Intel has the bucks to hire more gurus on the topic if they need them."

    That would be all well and good, if we were actually discussing a RISC architecture. But we aren't - we're discussing VLIW.

    With the i960 and crew, Intel has all the RISC expertise that they ever wanted (or needed). Finding someone who can write compilers and tools for VLIW is a horse of a different color, however. There isn't much experience in the industry when dealing with VLIW; not only that, coding for RISC isn't going to help you with this type of architecture. Hence, the hair-pulling and delays from the compiler/tools group. This isn't a problem you throw money at to make it go away faster - it's a first run, and everyone on the team is learning as they go.

    If that doesn't convince you, keep in mind that Intel is partnered with a company that has deep experience with RISC architectures (HP). If HP and Intel together are having a rough time of it, I would submit that this can't be an easy design to work with - especially given that no one has done it before.

    --
    -- ultra1
  8. Merced Is NOT For You by zealot · · Score: 3

    Too many web sites (especially gamer sites, for some reason), don't seem to understand that Merced isn't for the average user. When it comes out, and at the very least for a few years following, it will be an ENTERPRISE level chip. This means 1) expensive as hell 2) used in supercomputers (a la SGI and HP) and 3)high end workstations/servers. The author of this article is right... it doesn't fit into Intel's business strategy for the consumer, but it isn't supposed to. Besides, I'm starting to get the feeling that by the time Merced is consumer viable, people will be using pure computers less, and computing appliances more.

    --
    He said, "You'll be able to tell your grandchildren that you helped assemble the first NT supercomputer," and I cringed.
  9. Don't really see the problem here... by Roundeye · · Score: 3

    I'm not sure why this review was written.

    Intel has been plagued for a decade by backwards
    compatibility with a poorly designed CISC chip
    with one of the poorest memory subsystem designs
    still in current use. The amount of juice which
    can be squeezed from the '86 lemon is limited and
    it is a testament to Intel's determination (some
    would say stubbornness or stupidity) that they
    have been able to make this architecture a
    profitable industry standard (of course the more
    cynical (myself included on the occasional lonely
    night) might chalk this up as a testament to the
    power of a tightly run monopoly).

    Merced is a necessity if Intel wants to stay
    profitable in the face of not only Moore's Law
    but AMD and other not-so-dark horses. This chip
    has been designed for the most part for years.
    The compilers have been under development for
    years as well -- anyone who thinks otherwise
    doesn't know how Intel does business.

    A company which has the resources to write
    compilers for superscalar CISC with pipelining,
    data forwarding, bizarre MMX
    registers/instructions, virtual '86s while
    maintaining backwards compatibility with the
    original broken design will find writing a new
    compiler for a freshly designed clean RISC
    system a wonderful relief. The amount of
    openly available published research in the RISC
    compiler community is significant, and Intel has
    the bucks to hire more gurus on the topic if they
    need them.

    Marketing... It pains me to see so many people
    assume that "they way it is" is "the only way
    it can work". This is the same fallacious
    thinking that makes it painful to watch any
    Hollywood movie about time travel or the contact
    of our civilization with another (I think
    Indpendence Day may be the flagship example of
    this) -- the way we Americans do things in this
    day and age is superior to the way any other
    conceivable society could do them. Cultural
    ignorance and arrogance.

    This sort of thinking comes up quite often in
    discussions of why "Windows will be here forever"
    and now appears here in a discussion of Intel's
    marketing plan for Merced. The truth of the
    matter is that (1) Intel wants the market to
    change -- they have been burdened with the '86
    albatross for far too long, and (2) the market
    will change. Initially we hardware power users,
    systems hackers, and speed/systems freaks will
    jump on Merced because it is a better chip than
    a crappy CISC chip on steroids. The chipsets
    to run the chips will be there, and at least
    some variation in motherboard configurations.
    Dell/Compaq/Gateway will be able to sell a
    Merced system.

    If, as Intel puts more of its weight behind Merced
    (and more applications are brought to Merced) the
    current distribution system cannot change their
    marketing model to take advantage of the new
    configurations which will be possible and then
    *desired*, then someone will step up to make the
    new money by providing them. Because it's done
    a certain way now doesn't mean that that is the
    only way (I reiterate at the risk of sounding
    pedantic). This industry moves too fast to coddle
    companies which have become too large to steer
    effectively.

    The distribution channels for these systems, and
    multi-processor systems, will develop and may
    not include the current Big Players in the market.
    In addition, as Intel hopes, if AMD et al cannot
    create a chip to compete with Merced, and cannot
    anchor the market on the '86-type chips, they
    may also find themselves too big to steer out
    of the way of the Intel truck.

    Be careful. Merced could be a swan song for
    Intel, but I think it is more likely their
    Excalibur.

    --
    "Cause there's 40 different shades of black, so many fortresses and ways to attack, so why you complainin'?"
  10. Extra CPU's by Tardigrade · · Score: 3

    As long as Intel and the OEM's keep selling single-cpu boards, selling extra cpu's instead of entire systems shouldn't be too much of a problem. Most end-users don't like swapping mobo's and cpu's.

    Most users don't need the horsepower of their current K6-350, or PII-300, I'm still using a P-133. How much of their sales are going to be towards companies that can afford a hardware guy, or hard core gamers who have the skill and motivation to do this though? That might be a problem.

    That would also be enough motivation to keep on churning out a more advanced, speed and instruction-wise, processor though. Intel has been pretty good at making a new cpu ever 3 years or so, the average time between upgrades. They've been even faster with the improved chipsets. The rest of the computer has gotten better as well.

    As long as it's more expensive to build/upgrade to a state of the art system, I don't think the OEM's will have too many problems. Everyone, especially the hardcore gamers, know that the cpu isn't everything. The compiler is another story, but that'll happen too.