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New RAM technology developed
Christopher Thomas writes "Tom's Hardware Guide had a link to this EE Times article, which describes a new type of RAM developed by Hitachi. It uses stored charge in what looks like a cleverly controlled floating gate to store data, as opposed to stored charge in capacitors in conventional DRAM. Hitachi says that it will be able to ship this in quantity reasonably soon. It looks reasonably compact, and will scale much more easily to smaller linewidths than standard capacitor-based DRAM cells. It's also faster, as you don't have the whole precharge/amplify readout cycle to deal with. "
As to the statement...
:-)
"...It's also faster, as you don't have the whole precharge/amplify readout cycle to deal with. "
This is probably not true. Precharge and amplify has less to do with nature of the memory cell,
but are used to speed up the access time of a RAM device. Even today's fast static-RAMs use
precharge and amplify circuits to speed things up. (DRAMs also use the sense amps to restore the
capacitor charge on read cycles, but SRAMs usually don't need this function, but still have amps
for speed).
The precharge is to put the bit sense lines into a known state (as opposed to an unknown state).
Once the bit cell starts driving the bit sense line the sense-amp, senses the small change from
the known state and amplifies it. If you don't precharge, you have to wait a while for the data
to stabilize. But if the bit sense lines are precharged to a known state, as soon as it starts
to change one way or the other, the amp kicks in and bam!
Also in a large (eg, Gbit arrays) the poor little super-small transistor that is attached to
a bit of the memory in the middle the array has little hope of driving a big long piece of
bit-sense wire out to the edge of the array without the help of an amplifier
In a word, no. Sram uses latches. Capacitor eq: C = keA/d.
k = dielectric constant, 3.9 for SiO2.
e = permittivity of free space, 8.85e-12 F/m
A = area of plates.
d = distance between plates.
Solution? Make d really really small. The capacitance values are only a few femto-farads (1e-15) anyways.
http://www.ryans.dhs.org
DRAM is a funny thing. You read these wide rows out of the DRAM array (usually 2K bits) using
:-)
what is called the row address by an amplifier (called a sense-amp). This takes a long time.
After reading, all 2K bits are fed-back on the sense amp (kinda like a cache for the row). Now
once the row is read, you can just switch out the data for a column address really fast (say 6ns).
But, if you need a new row, you have to go back to the slow row access.
But you really don't get 6ns column access time either. To top it off, today's SDRAMs are
pipelined (the S is for syncronous). This means you have to send in the address 2-3 clock cycles
ahead to get the data. You can still get new data every 6 ns in a burst, but you have to figure out
things a couple clocks in advance (i.e. random access will suck).
Trac -> access time from new row address (or SDRAM activate command) say 50-100ns
Tcac -> access time from column address (or SDRAM read command) say 5-20ns
R/W times have always been slow to DRAM arrays, but DRAM architects have been pretty good at
hiding it
?. This is completely different from the definition that I heard. The type of "bubble memory" that I know about stores data in isolated magnetic domains (bubbles) that can be physcially moved around within a crystal. High density, but serial access (though you can get around that to some degree). I'm told that it was also slow and sensitive to external magnetic fields, but other sources say that those problems were solved.
Addendum: This works for conventional DRAM too. However, I gather that it isn't done (except possibly for Virtual Channel Memory). A static transistor instead of a capacitor would still give you better signal strength, though.
I think this technology is what makes the
new Sony Playstation-2 fly.
What's *MOST* interesting about this IMHO is
that it allows you to integrate dense, fast
RAM onto the same chip as dense, fast logic.
With normal DRAM technology, something to do
with the fabrication process makes it hard to
get lots of logic circuitry onto the same die.
So, when the RAM and the CPU (whatever) are on
the same chip, you are suddenly not limited in
speed by the width of the bus between the two.
With two separate devices, you can't really get
more than a couple of hundred wires of less than
a couple of inches long. With this technology,
the Playstation-2 chips are using 2560 bit-wide
busses - probably no more than a couple of
millimeters long - resulting in truly spectacular
overall memory access times.
For 3D graphics, this is an extremely important
advance that permits architectural changes in
the system that are *MUCH* more significant than
the raw density, cycle time or cost figures would
suggest.
Exciting stuff.
Although the fabrication technology for the chips inside the Sony PS2 hasn't been finalized,
:)
they are going to use what is called a hybrid process (logic and DRAM on the same die) to make
an chip with embedded DRAM. Today's technology allows about 4Mbytes of DRAM to be put on a chip
with the left over space used for logic. Yes, hybrid processes are a bit less efficient than all
logic or all DRAM processes, but are catching up (about 1 generation behind)...
Hybrid processes are currently the state of the art and allow cool things such as embedded DRAM.
(which allow really wide busses and fast access) However, the memory is still capacitors and
transistors, for standard DRAM not this wacky new stuff (but one of these days...).
(oh, and -yes- I know what I'm talking about here...
This actually isn't terribly relevant to the topic. There was, IIRC, only a single mention of the new type of RAM developed, as a tangential point. While the post was interesting, I can see why it was rated down.
Nothing remotely amusing can be allowed past the moderators though.
For all of the whining that goes on, I have yet to see something moderated down that didn't deserve to be. I do read at -1, so I see everything.