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HP & IBM Unveil New Chips

Posted by justin++ on from the let-me-guess-"beowulf!" dept.

In the CPU market, both IBM and HP have new offerings. The first chip is IBM's 500-MHz PPC 440 for embedded systems, etched at .18 microns, and the second is the HP PA-RISC 8600, which uses the same core as the 8500. The IBM chip is for embedded applications, while the second is for workstations. The HP debuts at 500 MHz, and will soon be followed by the 8800.

2 of 69 comments (clear)

  1. Re:PA-RISC and iTanium by Guy+Harris · · Score: 4
    Anyways, since HP had a hand in with Intel in designing the Merced, will it also be able to emulate PA-RISC based software in addition to x86 software?

    Not by itself; the code would be translated to IA-64 code by software. This part of HP's versionof the IA-64 Application Instruction Set Architecture Guide says:

    Binary compatibility between PA-RISC and IA-64 is handled through dynamic object code translation. This process is very efficient because there is such a high degree of correspondence between PA-RISC and IA-64 instructions. HP's performance studies show that on average the dynamic translator only spends 1-2% of its time in translation with 98-99% of the time spent executing native code. The dynamic translator actually performs optimizations on the translated code to take advantage of IA-64's wider instructions, and performance features such as predication, speculation and large register sets. In addition, if an application has been aggressively optimized for PA-RISC, some of the benefit of the optimizations will carry over to IA-64. In fact, an aggressively optimized PA-RISC application may actually perform faster on IA-64 using the dynamic translator than the same application recompiled at a low level of optimization on an IA-64 compiler. Of course, the best performance will result from a high level of optimization using a good native compiler.

    The dynamic translator is designed to run all non-kernel intrusive code, handling both 64-bit and 32-bit instructions. This means operating systems and device drivers typically would not be supported, but all other applications will run. HP's dynamic translator will be bundled with all versions of HP-UX sold for IA-64 systems. When HP-UX encounters code compiled for PA-RISC, it will automatically and transparently invoke the dynamic translator which will allow the code to run on IA-64 without any intervention. Correctness of the dynamic translator has been verified with the same testing regimen used to validate PA-RISC processors.

    If I remember correctly, HP used binary-to-binary translation to move code for the stack-based 16-bit HP 3000 machines to the PA-RISC-based 32-bit HP 3000 machines, so they've done this before.

  2. Re:PA-RISC and iTanium by Guy+Harris · · Score: 4
    I believe either Merced or McKinnely will have NATIVE PA-RISC support, rather than emulated support as is the case of x86...

    "Native" and "emulated" in what sense? Merced (and, I suspect, McKinley) will be able to directly run x86 code; in what sense is that "emulated" rather than "native"? (The latest Microprocessor Report has a story on Intel's presentation on Merced at the latest Microprocessor Forum; it says

    Sharangpani's presentation shed little new light on Merced's IA-32 portion. As disclosed earlier, IA-32 code and data share the same caches and execute in the same function units. [Presumably "same" means "same as what IA-64 code and data use". -gh] When in IA-32 mode, the processor fetches x86 instructions into a separate decoding and scheduling unit that reorders the instructions and executes them using the native execution core. [The article doesn't say that they'll be translated to native instructions. -gh] We expect the IA-32 decoding and scheduling unit to be similar to Pentium III's front end.

    As for PA-RISC code, HP's IA-64 documentation online (see my other comment in this thread for a reference) says that the chip won't execute PA-RISC code; software will translate PA-RISC code to IA-64 code, and the IA-64 code is what will be executed. In what sense is that "native" rather than "emulated"?

    A while back, I did some calculating of chips based on their SPEC performance, and MHz for MHz, the PA-RISC series is the fastest line of chips.

    But if it's easier to make, say, a 21264 run at a given clock rate than it is to make a PA-8500 run at that clock rate, "Alpha wins in the end" regardless - SPEC/MHz isn't necessarily a figure of merit in and of itself.