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Intel squashes Rambus Bugs

Posted by Hemos on from the squash-squish-squash-squish dept.

Fooster writes "According to this article in Forbes, Intel has indentified and solved the problems in the i820 chip for Rambus. Few details on the nature of the solution. " As Forbes points out, the challenge is getting OEMs back on board - I'd be skittish as well.

4 of 77 comments (clear)

  1. Current Technology is Good Enough by ecampbel · · Score: 3

    Rambus is another causality in the PC world where the best technology seems to get passed up for either the current technology or cheaper technology. The best technology doesn't necessarily dominate. The MacOS is a good example of this, as is the FireWire bus. Despite Intel's backing I would bet that this technology will only be used is niche market of high-end servers. The $200 PC's of the world will never want to pay a premium for a small increase in performance. The current SDRAM technology will be tweaked for years to come, and Rambus will never be the dominant standard.

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  2. It's the latency stupid by severian · · Score: 3
    I think that regardless of whether Intel fixes the RamBus bugs or not, it's a poor technology. The problem with memory speed breaks down to two issues: latency and bandwidth. Although everyone salivates at the thought of enormous bandwidth, in today's systems, what really causes problems is memory latency. And ironically, although RamBus promises higher bandwidth than SDRAM, it's actually has *higher* latency.

    There are some great articles regarding bandwith vs. latency in general and RamBus in particular at Tom's Hardware. To summarize the articles, even today's current SDRAM architecture provides more than enough bandwidth, especially with the current sophisticated cache systems that reduce memory accesses dramatically. However, what's tying up the CPU is latency, especially as CPU's get faster.

    In other words, CPUs generally request small amounts of data with any given request, but it has to wait a long time for that request to get back. As CPU speed has increased, better cache systems have mitigated the resulting increased bandwidth demands but nothing has helped the resulting latency problems. So the way to speed up memory is to decrease latency and don't worry too much about bandwidth just yet. Unfortunately, RamBus goes in the exact opposite direction.

    That said, I guess we should never underestimate the power of a behemoth like Intel to force acceptance of poor technologies :-/

  3. Fix or Band-aid? by overshoot · · Score: 3
    From what I've gathered of the signaling problems with Rambus there are only two main ways they could 'fix' the present problem, and neither is exactly a fix.
    • Increase the trace separation to reduce the crosstalk and pattern-dependent impedance mismatches. Along with this an adjustment in termination resistance might be some help.
    • Change the trace lengths to move the resonant point away from the line fundamental frequency. Apparently a resonant mode near the signaling rate was one of the main gotchas.

    In both cases new motherboard layouts will be needed, and since both will take up more space the whole floorplan may change. At best, this will take a few months to get the MBs designed, through validation and regulatory approval (not a trivial issue with this kind of bandwidth!) and into the production pipe. Kiss Q4 goodbye and probably Q1; the memory shops won't be seeing any demand until Q2 at soonest, if at all.

    On top of that there will always be the charming issue (which Rambus seems to have in other areas as well) that the operating area for the memory subsystem will have a Swiss-cheese character. Instead of a 'schmoo' plot, with a maximum frequency of operation and constraints on voltage and temperature, there will be areas of operation and failure, alternating. Maybe 300 MHz and 800 MHz will be OK, but 700 will be out. In fact, that seems to be the situation right now.
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  4. Road to Nowhere by SlydeRule · · Score: 3
    I'm not clear on how Rambus is supposed to be "the next step in the chip-set food chain".

    Intel has (IIRC) said that Rambus won't be used on Celerons, won't be used on 100-MHz FSB P-III's, won't be used on Xeons, won't be used on Itania (no I won't say Itaniums), and won't be used on systems with more than two CPUs.

    So here we have a memory technology which is limited to 1- and 2-processor 133-MHzFSB Pentium III's. Those systems don't need Rambus, since they can work with PC-133.

    Rambus claims to be faster than PC-133, but over and over again the benchmarks refuse to confirm that.

    Where's the future in Rambus?