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Tiny New Chips Win ChipCenter Award
phi1o writes "Ever wonder why a burrito-sized pentium is also called a "micro" chip? Me too... This page @ ChipCenter shows a new line of chips from National Semiconducter that are *really* small. They're all analog and of course nowhere near as complex as a P3, but you gotta wonder if processors are headed down this road in the future, to where they are mostly silicon rather than ceramic and plastic. On the one hand, this will make for smaller devices. On the other, it's gonna make building anything without a giant factory (ie in your bedroom.... hardware geeks with me?) much more difficult. I don't know what to think. "
This looks like a very good thing. By focusing on shrinking the package as opposed to the trace size, they avoid the costs associated with building new fabs to support the shrunk designs. Additionally, by incorporating the package on the wafer and eliminating manufacturing steps, it should be very attractive to implement.
Provided that the tech can scale up, and that the market adopts it, it could be a big step towards super-small devices embedded in just about anything.
Let's see...a microcontroller, a temp sensor, and a d-a converter in a 3-pin-head size. Stick that in your shirt and you've got something that beeps when you get hot under the collar!
Of course, when they come up with a CCD and a couple megs of RAM on the head of a pin, that's when I'm going to worry.
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These are "smart" sensors, each of which has a unique 64-bit address, up to 254 of which can reside on a single pair of conductors that can be up to 300 meters long.
There are obviously many different kinds of chips but for processors and ASICs the trend is towards larger and larger die sizes. The three main factors in this are 1) need for more I/O and power pins, 2) Advances in semiconductor processing facilities and equipment have reduced defect density over the years to make larger chips practical, and 3) For processors especially, an increasing fraction of the chip is memory which can be protected to a large extent by redundancy.
The eight bit micros like the Z80, 6800, and 8080A had die sizes of around 20 - 22 mm2 and 40 pins. In the 16 bit era the die sizes were around 40 to 80 mm2 and pin count ranged from 40 to 68. The early 32 micros like the 68020 and 386 were about 85 to 100 mm2 in size and used 114 to 132 pins.
In the start of the modern PC era the emphasis was on performance and features and die size was pushed hard with the anticipation of multiple process shrinks to allow the part to enter the manufacturing sweet spot of around 100 to 150 mm2 for inexpensive and high volume production.
The Pentium and Pentium Pro (P6) were both introduced around 300 mm2 but didn't reach high volumes until shrunk into more advanced processes.
The Pentium shrank from 306 mm2 in 0.8 um, to 163 mm2 in 0.5 um, to 91 mm2 in 0.35 um (with caches doubled in size and MMX added).
The largest processor today is the PA-8500 which checks in at a whopping 475 mm2 in 0.25 um. But remember this chip is nearly 3/4 cache SRAM (1.5 Mbyte). The 8500 is probably the largest chip that can fit in the field of exposure with the current generation of optical steppers.
We can expect mainstream processors to get larger in the future because of the trend towards integrating level 2 and even level 3 caches on-chip. Memory redundancy makes these larger chips practical while the growing disparity between fast wide issue CPUs and main memory performance makes large on-chip caches mandatory. For embedded processors and CPU cores in system on a chip type applications the die size is typically kept from shrinking much below 50 mm2 by bonding pad spacing requirements ("I/O limited").
-Why are you searching the carpet with a magnifyng glass?
-I dropped my laptop.
You are the same decaying organic matter as the rest of us.
"Whatever else you are told to believe,
do not accept that size is unimportant"
Yeah, we hear *that* one all the time. So what are you saying?
Oh, smaller is *better*? Yeah, those nerds use *that* excuse all the time.
Any female slashdot readers out there want to confirm or deny these
accusations? And what about that bit with the standard mounting process,
do you liberated women agree with that too? And... hey, is this segfault?
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pb Reply rather than vaguely moderate me.
pb Reply or e-mail; don't vaguely moderate.
"Teacher, I couldn't finish my homework because the cat swallowed my computer."
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My mom's going to kick you in the face!
(ie in your bedroom.... hardware geeks with me?)
.5 mm apart or less, or somehow solder an entire array of contacts simultaneously while they sit between the board and the chip.
It's allready getting hard to do hardware hacking with anything much more than an 8 bit processor. I think you can still get a 68000 in a 64pin DIP, but everything else is heading to QFP, TSOP, and worst of all BGA. To work with these you either have to solder wires spaced
It's because of things like this that I have very few designs on building any sort of major computing device in the near future.
Start Running Better Polls
Microstepping an XYZ gantry to move a vacuum-needle pick-'n-place, with a single-jet droplet depositor for flux coming before and a hot-air solderer coming after, more or less on the same toolhead... definitely the kind of thing a linux box can be programmed to drive (with a couple of dirt-cheap MCUs -- 8052? -- for the critical-timing stuff such as the actual pulses and the microstepper control)..
:)
Yeah, I could see something like that in the freehold utility room
Seriously, whikle this stuff will be as pervasive as present surface-mount is now (it's just SMD taken all the way), clunky old thru-hole devices won't go away entirely, they'll just get pricy, probably, because they'll be used mainly for prototyping.
If I visualize this correctly, one downside to the naked chip-on-board technique these packages use is thermal-related fracture: the silicon has far less flex than the leadframe it replaces, so the board the package is bonded onto better have the same thermal expansion as the chip, the chip will fracture or tear loose a few bonding-blobs otherwise.
The Garage/bedroom hardware hacker is, for the most part, dead.
There WAS a time when you visited 3M's surplus, bought dead boards by the pound, desoldered the chips and tested the gates individually.
Then you built your own machine.
As we moved from MSI to VLSI (and beyond), the hardware hacking oppertunities have become the thing you do if you have a simple project (and you can reduce them to a PAL or perhaps a FPGA).
Because the OLD method was:
Design on paper
Build the prototype
Look for errors
put the logic scope on to find the errors
loop to build prototype till fixed.
(Anyone wanna buy a CP/M based logic analyzer prototype? one of 10 in the world)
The *NEW* method is
Design on computer in test environment
Test on computer
Build on silicon
Do a bit of testing (cuz it should work on the 1st time)
Ship.
*IF* you are looking to be a Hacker:
Software hacker - get machines thrown out in dumpster, and old software you beg, borrow, or GPLed $0
Hardware hacker - newer machine, DSP or FPGAs, prototyping boards, software (hard to have GPLed tools here) - $5000-$25000-How deep are your pockets...
Being a bedroom/garage hardware hacker is no longer cheap, and based on simple tools, like it used to be.
Software hacking is the last low-cost (Bedroom/garage) hacking frontier. You may not be as productive with cc and make as you are in an intergrated environment, but tools are only part of hacking..the grey matter you have to manuplate the tools matter most.
If it was said on slashdot, it MUST be true!