Sun's MAJC vs Intel's IA-64

Shauna writes "Ars Technica has an informative article on the differences and similarities between Sun's new MAJC and Intel's IA-64 plans on the design-level. I think it shows in a round-about way that MAJC is going places while Intel sleeps. " The article is definitely designed for the chip fetishists in the audience.

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More info

[ChrisRijk]

MAJC developers connection

A chat with the lead designer for the MAJC architecture

MAJC 5200 chip press release From MAJC docs page: First MAJC implimentation presentation.

Some comments... Firstly, I don't think it was made clear that the MAJC architecture can execute compiled C/C++ as easily as Java. You'd also probably be using a dynamic compiler like HotSpot rather than a JIT compiler. I think the guy got it wrong about the functional units being data agnostic - the registers definately are though. Still, you can (pretty much) execute 4 of any type of instruction at once - the first block is slightly different compared to 2-4 (which are indentical), though I don't know how. The very interesting STC concept is much easier to do with the Java programming model (because of certain issues with data) compared to C/C++. They don't say how easy it would be to apply STC to C/C++ though - might be impossible in the general case, though possible in some "limited" cases. The MAJC does also have scoreboarding for instructions for dynamic execution times eg loads, though I'm not sure if this applies to things like FP multi/div/sqrt etc. There's a couple of other interesting things the guy missed - the cross-bar data switch and the steaming data ports, for example. Though apart from that, I think it was a pretty decent review.

With regards to the first chip - the MAJC 5200, it's supposed to "tape out" (get first physical implimentation) by the end of the year and sample in Q2 next year. The 5200 has 2 CPU units on chip (with a shared L1 data-cache and a seperate L1 instruction caches), will be made on a .22 micron process, run at 500Mhz and consume 15W.

Here are some "here's how fast it is" stuff from the PR:

• This chip is expected to be able to handle over one hundred voice-over-IP channels while enabling encryption and decompression of the packets over a 10 gigabit-per-second Ethernet connection. This means that a very large number of simultaneous phone conversations could be supported in a small-footprint gateway server device. In the area of image processing, the JPEG 2000 test set is anticipated to run at 78 MB/s while encoding 8-bit sample images. For networked video, two streams of MPEG-2 data representing five Mbps interlaced sequences have the ability to be simultaneously decoded, with additional processor capacity still available. For teleconferencing under the H.263 standard, six decodes and one encode are expected to be handled in real time. In advanced audio applications, an AC-3 decode of 5.1 channels at 384 kps is predicted to use only seven and one-half percent of the capacity of one of the 5200's two processors.

btw, Sun have a 2000 processor array for simulating their UltraSparc-III chip and they do do some pretty accurate simulations, including things like booting Solaris. In the MAJC 5200 PDF/PS file, they also quote some (estimated) speed-ups gained from using the STC technique for the SPECjvm98 suite of programs - they get from 40-60% or so, which I think is very impressive. The MAJC 5200 also has a graphics pre-processor (it's going to be used in Sun's new high-end graphics systems) and they quote some triangle processing figures with different levels of lighting detail. I don't really get what they mean, but they quote from 60 million triangles/s to 90M/s or so, which is in about the same region as the PlayStation2, or about 4x faster than the fastest current mainstream PC graphics card. However, that doesn't mean you can use 60m-90m in real world stuff...

In general, the chip is aimed at "low end" (though for Sun, "low end" equates to less than $100,000 generally) embedded solutions.