I consider the relation of anti-establishmentarianism and "amoral drug" use to be the dogma of established anti-establishment.
Just as Nancy Reagen keeps telling me how bad the amoral drugs are, so do Phillip K. Dick and William Gibson and Robert Anton Wilson tell me the opposite.
I am not a wireless expert, but to be it seems like there's a bandwidth problem. For wired communication, if you want more bandwidth, you just lay some more lines (examples: interleaved memory banks to increase memory bandwidth, laying more fiber to increase WAN bandwidth).
But with wireless, there's only so much bandwidth in the ether up there! And information theory tells us there's only so much lossless compression we can expect, right?
I agree. Retention, I think, is one of the most important aspects of learning. The more stuff you remember, the more likely you are to make non-immediate connections.
I think imperative languages are considered to be something of a dead end of optimization only by people who spell optimization with an "s" instead of a "z".
I thought Manhattan Scientifics owned the patent on the Los Alamos mini fuel cell? The yahoo article implies (to me) that Motorola is using the same technology, but makes no mention of MHTX. What's up??
(made a good chunk of change on MHTX! 1.4->6.4, yippee!).
dangit! I always post too early. I meant to add that most commodity SMPs don't concurrency-match well at all. In fact, the concurrency of most commodity SMP subsystems is about 1!
In contrast, the concurrency of "good" SMPs, like the convex exemplar or origin 2k is huge. For example, the exemplar has (can't remember exactly) like 8 banks or 32-way interleaved memory, attached to processors over a crossbar!
And all this concurrency for a measily 16 processors:)
I've said it once, and I'll say it again! The biggest bottleneck for SMPs is the concurrency supported by the cachememory link. Not bandwidth, not latency, not capacity, concurrency.
If you don't match the concurrency of your memory link with the concurrency of your clients (i.e. processors), you're hosed for any demanding application.
What do I mean by memory link concurrency? It could come from crossbar versus bus, or multi-ported memories, or from multibanked (interleaved) memories.
Cray has zillion-banked memories. Processors now have multi-banked caches, because there are lots of things going on at once inside out-of-order issue processors!
Hiyo. I think the original post was ambiguous. It could either mean insanely idiotic (OS and component) licensing schemes, or insanely idiotic (OS) and (component licensing schemes).
If the former, I agree with the original poster. If the latter, then I'm with you.
The Pentium Pro had an on-chip, but separate die, L2 cache. The Ppro "chip" actually had two dies. Still ran at full speed, though. Being off-die, they had to limit the line size to 32 bytes.
In contrast, the Celeron, Alpha, R10k, and I guess these new P3e's have on-die L2 caches.
hehe, that's the cool thing about slashdot, you never know who you'll meet!
I agree that LeGuin and Delany did not have a common vision. I recall reading a work on the net which puts these three books as a trilogy: Heinlein's The Moon is a Harsh Mistress, The Dispossessed, and Triton. I would also add in Joanna Russ' The Female Man.
All four paint a picture that anarchy must be displaced (i.e. a utopia must be heteropic), and that it must be in conflict with "normal" society.
Where they differ is in the interplay of technology and utopic society. Russ and LeGuin seem to say that they are at odds, while Heinlein and Delany say something else. Though Heinlein and Delany differ, as well.
Are you familiar with Michel Foucault's terms "heterotopias" and "panopticons"? He takes the former from the medical term meaning to take one part and place it in another (unnatural place) as a substitute; e.g. skin graft, sex change.
DisneyWorld is not a utopia, but a heterotopia. It is a mirror, a place which stands apart from the rest of society so that we can gaze into the depths of our society's soul.
Samuel Delany's Triton and Ursula K. LeGuin's The Dispossessed both give different pictures of heterotopias. Delany uses advances in technology as part of this mirror. Perhaps it is more of a prism, though.
If you want more depth on Delany's "prism, mirror, lens" metaphors, he uses them through his work, but the figure prominently in Dhalgren.
HotSpot is Urs Hozle's work. He's a professor at UC Santa Barbara, but is a visiting scholar at stanford, as well as being the CTO of a company and working with Sun.
You can claim any algorithm scales if you have a simplistic enough performance model. Naively implemented (i.e. without concern for cache locality) sorting scales relatively well using a uniform memory access cost model, but very poorly using a nonuniform memory access model.
Teehee, I noticed that I submitted that post a little early. Let me finish the unfinished sentence in third paragraph:
... with communication-bound algorithms] your speedup is limited by Amdahl's Law. As most good laws, it's pretty simple to state: the best parallel efficiency you can expect is bounded by the amount of time spent doing serial stuff.
So, with an embarrasingly parallel algorithm, you're set! But, an algorithm which has lots of communication is doomed on two fronts: first, Amdahl's Law hits it due to the amount of communication (time spent doing zero computation!), and second, commodity SMPs, get a further hit due to poor memory hierarchy design: once the algorithm strays beyond L2 cache, the application is serialized.
Certainly some applications are embarrasingly parallel (aka "data parallel"); that is, after a tiny bit of startup cost, your speedup is only limited by the number of processors and the size of the problem (amount of data).
Examples of data parallel problems: image rendering, key cracking, matrix-matrix and matrix-vector multiplication.
However, many applications are not embarrasingly parallel; that is, the processors must communicate (aka synchronize) at certain points, in order for the computation to proceed. Here, your speedup is limited by the
Examples: sorting, matrix factorization (e.g. LU decomposition).
In my experience, commodity Intel motherboards scale very poorly for this latter class of problems. Why? If the two threads always hit their L2 cache (i.e. don't have to fetch across the memory bus to main memory), then everything might be ok. (even then, write sharing can cause cache thrashing!). If the threads must fetch miss L2 cache often enough, then (on commodity motherboards), the threads will be serialized, because the memory is not interleaved, nor multi-ported.
On fancier (expensiver, hehe) SMPs, processors are connected to either interleaved, multi-ported memory, or over a crossbar (rather than a bus), or probably all three. For example, the HP Convex Exemplar ($$$) has all three.
On a counting (integer) sort, a 2-processor commodity SMP is limited to 1.4/2 speedup (roughly the fraction of memory references which hit cache). The convex gets speedups of 1.95 (limited only by the tiny startup costs, as in the embarrasingly parallel case).
A neural network is nothing more than a formalism for nonlinear curve fitting. It can't magically solve problems any faster than any other (conventional) technique.
On the other hand, quantum computation, like biological computation, can solve a certain class of problems much faster than conventional computers.
For example, quantum and factorization, biological and string matching.
Noone that I am aware of has shown that quantum or biological computation can solve a general class of problems faster.
Slashdot Mirror
They won't name it version 1.0; it'll be at least 3.1
nick
I consider the relation of anti-establishmentarianism and "amoral drug" use to be the dogma of established anti-establishment.
Just as Nancy Reagen keeps telling me how bad the amoral drugs are, so do Phillip K. Dick and William Gibson and Robert Anton Wilson tell me the opposite.
I believe neither.
I am not a wireless expert, but to be it seems like there's a bandwidth problem. For wired communication, if you want more bandwidth, you just lay some more lines (examples: interleaved memory banks to increase memory bandwidth, laying more fiber to increase WAN bandwidth).
But with wireless, there's only so much bandwidth in the ether up there! And information theory tells us there's only so much lossless compression we can expect, right?
How far away are we from saturating the ether?
nick
nick
I agree. Retention, I think, is one of the most important aspects of learning. The more stuff you remember, the more likely you are to make non-immediate connections.
nick
I thought Mach was the microkernel (i.e. IPC, protection, hardware abstraction), and BSD was the userland (i.e. filesystems, network, paging)?
thanks,
nick
I think imperative languages are considered to be something of a dead end of optimization only by people who spell optimization with an "s" instead of a "z".
:)
Your American Imperative Optimizer,
nick
What a second. what's the difference between a "module" and a "driver"?
Hi UL: who are the Inheritors of Iridium?
(eheh, sounds like a corny sci-fi book)
but seriously...
thanks!
I thought Manhattan Scientifics owned the patent on the Los Alamos mini fuel cell? The yahoo article implies (to me) that Motorola is using the same technology, but makes no mention of MHTX. What's up??
(made a good chunk of change on MHTX! 1.4->6.4, yippee!).
nick
dangit! I always post too early. I meant to add that most commodity SMPs don't concurrency-match well at all. In fact, the concurrency of most commodity SMP subsystems is about 1!
:)
In contrast, the concurrency of "good" SMPs, like the convex exemplar or origin 2k is huge. For example, the exemplar has (can't remember exactly) like 8 banks or 32-way interleaved memory, attached to processors over a crossbar!
And all this concurrency for a measily 16 processors
I've said it once, and I'll say it again! The biggest bottleneck for SMPs is the concurrency supported by the cachememory link. Not bandwidth, not latency, not capacity, concurrency.
If you don't match the concurrency of your memory link with the concurrency of your clients (i.e. processors), you're hosed for any demanding application.
What do I mean by memory link concurrency? It could come from crossbar versus bus, or multi-ported memories, or from multibanked (interleaved) memories.
Cray has zillion-banked memories. Processors now have multi-banked caches, because there are lots of things going on at once inside out-of-order issue processors!
It's all about concurrency matching!!
nick
I'm sorry it was a statement: PowerPCs are not out of order.
The question mark was me wondering why the poster thought they were.
Hiyo. I think the original post was ambiguous. It could either mean insanely idiotic (OS and component) licensing schemes, or insanely idiotic (OS) and (component licensing schemes).
If the former, I agree with the original poster. If the latter, then I'm with you.
nick
The Pentium Pro had an on-chip, but separate die, L2 cache. The Ppro "chip" actually had two dies. Still ran at full speed, though. Being off-die, they had to limit the line size to 32 bytes.
In contrast, the Celeron, Alpha, R10k, and I guess these new P3e's have on-die L2 caches.
PowerPC's are not out-of-order...?
Ok, ay caramba. Slashdot is really showing it's stuff, today.
:)
Yes, NP-complete and NP-hard are not synonymous.
So:
NP means "polynomial-time verifier".
NP-hard means "reduce to NP in polynomial-time".
NP-complete means "NP and NP-hard".
But, these all refer to classes of computable problems.
The halting problem is the prototypical "not computable" problem. Thus, it is not in NP-hard.
Hehe, I hope I got that right
nick
hehe, that's the cool thing about slashdot, you never know who you'll meet!
I agree that LeGuin and Delany did not have a common vision. I recall reading a work on the net which puts these three books as a trilogy: Heinlein's The Moon is a Harsh Mistress, The Dispossessed, and Triton. I would also add in Joanna Russ' The Female Man.
All four paint a picture that anarchy must be displaced (i.e. a utopia must be heteropic), and that it must be in conflict with "normal" society.
Where they differ is in the interplay of technology and utopic society. Russ and LeGuin seem to say that they are at odds, while Heinlein and Delany say something else. Though Heinlein and Delany differ, as well.
nick
Hi Mr. Katz,
Are you familiar with Michel Foucault's terms "heterotopias" and "panopticons"? He takes the former from the medical term meaning to take one part and place it in another (unnatural place) as a substitute; e.g. skin graft, sex change.
DisneyWorld is not a utopia, but a heterotopia. It is a mirror, a place which stands apart from the rest of society so that we can gaze into the depths of our society's soul.
Samuel Delany's Triton and Ursula K. LeGuin's The Dispossessed both give different pictures of heterotopias. Delany uses advances in technology as part of this mirror. Perhaps it is more of a prism, though.
If you want more depth on Delany's "prism, mirror, lens" metaphors, he uses them through his work, but the figure prominently in Dhalgren.
nick
HotSpot is Urs Hozle's work. He's a professor at UC Santa Barbara, but is a visiting scholar at stanford, as well as being the CTO of a company and working with Sun.
You can claim any algorithm scales if you have a simplistic enough performance model. Naively implemented (i.e. without concern for cache locality) sorting scales relatively well using a uniform memory access cost model, but very poorly using a nonuniform memory access model.
nick
Teehee, I noticed that I submitted that post a little early. Let me finish the unfinished sentence in third paragraph:
... with communication-bound algorithms] your speedup is limited by Amdahl's Law. As most good laws, it's pretty simple to state: the best parallel efficiency you can expect is bounded by the amount of time spent doing serial stuff.
So, with an embarrasingly parallel algorithm, you're set! But, an algorithm which has lots of communication is doomed on two fronts: first, Amdahl's Law hits it due to the amount of communication (time spent doing zero computation!), and second, commodity SMPs, get a further hit due to poor memory hierarchy design: once the algorithm strays beyond L2 cache, the application is serialized.
nick
Certainly some applications are embarrasingly parallel (aka "data parallel"); that is, after a tiny bit of startup cost, your speedup is only limited by the number of processors and the size of the problem (amount of data).
Examples of data parallel problems: image rendering, key cracking, matrix-matrix and matrix-vector multiplication.
However, many applications are not embarrasingly parallel; that is, the processors must communicate (aka synchronize) at certain points, in order for the computation to proceed. Here, your speedup is limited by the
Examples: sorting, matrix factorization (e.g. LU decomposition).
In my experience, commodity Intel motherboards scale very poorly for this latter class of problems. Why? If the two threads always hit their L2 cache (i.e. don't have to fetch across the memory bus to main memory), then everything might be ok. (even then, write sharing can cause cache thrashing!). If the threads must fetch miss L2 cache often enough, then (on commodity motherboards), the threads will be serialized, because the memory is not interleaved, nor multi-ported.
On fancier (expensiver, hehe) SMPs, processors are connected to either interleaved, multi-ported memory, or over a crossbar (rather than a bus), or probably all three. For example, the HP Convex Exemplar ($$$) has all three.
On a counting (integer) sort, a 2-processor commodity SMP is limited to 1.4/2 speedup (roughly the fraction of memory references which hit cache). The convex gets speedups of 1.95 (limited only by the tiny startup costs, as in the embarrasingly parallel case).
A neural network is nothing more than a formalism for nonlinear curve fitting. It can't magically solve problems any faster than any other (conventional) technique.
On the other hand, quantum computation, like biological computation, can solve a certain class of problems much faster than conventional computers.
For example, quantum and factorization, biological and string matching.
Noone that I am aware of has shown that quantum or biological computation can solve a general class of problems faster.
buy some DDS3 for $25. For $100, you get 60GB (uncompressed) storage on a tiny little tape that is probably more reliable.