The simple fact that travelling backwards in time would allow me to kill my former self, thus preventing me from ever having gone back in time to do so, is a complete logical contradiction, causes me to not care even in the slightest about this or that new theory which suggest FTL travel.
It just ain't possible.
Not strictly true. All that your example shows is that you would not be able to kill your former self. Two of the several solutions that I've heard postulated are:
Actions of time travellers must be consistent with observations.
Under this system, you would certainly not be able to kill yourself, becuase you didn't (you survived to travel backwards in time, didn't you?). This physically corresponds to limiting (drastically) the number of possible events that can occur within a loop of spacetime that folds back on itself in the time direction. This in turn means that such loops are entropically very unfavourable, but they could still in principle occur if a greater increase in entropy happened elsewhere.
Time travel is actually travel between multiple histories.
This refers to the "multiple histories" interpretation of quantum dynamics. Under this system, when you flip a coin, it lands on both sides - just in different universes. What actually happens is that all possible ways for a probability waveform to collapse happen, in different universes. If you travel back in time, you arrive in another universe, that looks a lot like the one you remember from that time - but in which a time traveller spontaneously appeared and killed the person who would have been you in your universe. This system doesn't impose entropic limits, but how exactly you travel between parallel universes is left as an exercise.
Both of these systems avoid the paradox that you menion.
This neatly solves the problem of "When the universe contracts, won't things get hotter and thus violate the law of thermodynamics?" No, because a contracting universe loses energy bacause objects get closer together and this again exactly offsets supposed increased energy as things get crushed together.
Actually, that's not accurate, if I understand correctly. As the universe contracts, GPE will certainly become more negative, but as a result of this kinetic energy goes _up_ for everything that's contracting. Thus, the universe gets hotter again.
(1) Objects far apart have more energy than objects close together (because it takes energy to separate them)
(2) The universe is expanding.
This just is just a statement that the total kinetic and rest energy of the objects in the universe has the same magnitude as the total gravitational potential energy of all objects in the universe. This is actually what _causes_ the universe to heat up as it contracts (and cool as it expands; the microwave background is a good example of this).
As an aside, the jury is still out as to whether the universe is really flat or not (i.e. whether or not this relation holds). We usually assume so because it answers a lot of questions, but we're having a hard time proving it.
it is possible and even probable that the entire universe is composed of a single electron in a parallel time frame for each instance (near infinite).
Actually, no. If only electrons and positrons and photons existed, then you might be able to draw a Feynman diagram with one line representing all electrons and protons, but beta decay takes care of that. A quark can decay into another quark, an electron, and an antineutrino. This provides the start of a new electron line. Similarly, a quark can decay into a positron, another quark, and a neutrino. This provides the end of an electron line. In principle, the reverse reactions could occur as well.
The article was very interesting, but I dont think its been refereed yet, so I wouldnt get excited yet. It seems to rely on "Alcubierre Space" (which I've not seen defined) being either wrong, or adjustable.
It's adjustable. If I understand correctly, "Alcubierre Space" is just one possible (and geometrically simple) configuration of spacetime that allows an object to (for practical purposes) "move" faster than light with respect to its surroundings. This is an extension and modification of those results that uses a more complicated geometry but has fewer practical problems.
Could someone go through the vast Slashdot archives and find 2 worthwile AC posts?
There was an excellent example a few months back. In one of the Free vs. Proprietary Holy Wars, an AC posted details of a lawsuit that his company was involved in as a thought-provoking case study. He (or she) would have been fired for doing this non-anonymously.
From what I can see reading at -1, maybe a third of AC posts are garbage, and most of the rest are at best average, but I see no reason to get rid of AC just because of the actions of a handful of twits. This is the second time that a lone idiot has spammed a thread. A solution that only attacks those twits would be nice.
Both banning IPs and limiting AC posts from an IP run into the problem of ISPs allocating IPs dynamically, and firewalls remapping users to a single IP address. However, it still might be the best solution (I'm open to other suggestions).
Or log IP and time for each post, so that Rob can contact the ISPs of abusers and get them LARTed. But that would be a lot of work for Rob.
Re:Above comment should not have been scored down
on
Rugged Laptops
·
· Score: 2
Where's the accontability in the moderation system here?
It's here in the form of rule-of-the-masses; if a moderator unjustly scores something, then other moderators will reverse it. This only applies if most moderators are fair, but it seems to have worked fairly well so far IMO.
Arrange a single RAM chip into multiple banks with a column height of 16 or 32 cells. Most of your die space is still taken up by memory, and your transistors only have the capacitance of a handful of other drains to worry about. This could be driven without amplification, and would still be quite fast. You even get many free row caches (one per bank).
Addendum: This works for conventional DRAM too. However, I gather that it isn't done (except possibly for Virtual Channel Memory). A static transistor instead of a capacitor would still give you better signal strength, though.
"...It's also faster, as you don't have the whole precharge/amplify readout cycle to deal with. "
This is probably not true. Precharge and amplify has less to do with nature of the memory cell, but are used to speed up the access time of a RAM device. Even today's fast static-RAMs use precharge and amplify circuits to speed things up.
I was referring to the sense amplifiers, which take a while to produce stable readings if I understand correctly. AFAIK precharge/amplify assisted circuits of the type you describe are faster, because they have a signal continuously driving them and so are less sensitive to noise. I could be wrong about this, but I don't think so.
Also in a large (eg, Gbit arrays) the poor little super-small transistor that is attached to a bit of the memory in the middle the array has little hope of driving a big long piece of bit-sense wire out to the edge of the array without the help of an amplifier:-)
If you connected hundreds or thousands of transistors into a column, this would certainly be true. However, I certainly hope that chip designers wouldn't do this. Arrange a single RAM chip into multiple banks with a column height of 16 or 32 cells. Most of your die space is still taken up by memory, and your transistors only have the capacitance of a handful of other drains to worry about. This could be driven without amplification, and would still be quite fast. You even get many free row caches (one per bank).
Ooh, someone with an opinion, yeah better moderate it down. Why not try to point out the logical flaws in the argument if you think its so stupid. After all it is relevent to the subject etc.
This actually isn't terribly relevant to the topic. There was, IIRC, only a single mention of the new type of RAM developed, as a tangential point. While the post was interesting, I can see why it was rated down.
Nothing remotely amusing can be allowed past the moderators though.
For all of the whining that goes on, I have yet to see something moderated down that didn't deserve to be. I do read at -1, so I see everything.
If I remember from reading a 1975 paperback on semiconductors, bubble memory was another name for a charged coupled device, or CCD.
?. This is completely different from the definition that I heard. The type of "bubble memory" that I know about stores data in isolated magnetic domains (bubbles) that can be physcially moved around within a crystal. High density, but serial access (though you can get around that to some degree). I'm told that it was also slow and sensitive to external magnetic fields, but other sources say that those problems were solved.
I've got three PCs running AGP cards just fine. AFAIK, AGP looks the same as PCI to Linux, only faster.
True. However, if I understand correctly, you won't be able to use system memory for texturing without explicit AGP support. This is one of the primary benefits of AGP (especially with cards that let you read triangle setup data from AGP memory; bus-limit bottlenecks just got a lot wider).
I don't know what kind of support this requires OS-side, but the previous post implied that AGP chipset specs are needed. Certainly the OS needs to be able to lock and unlock sections of memory for use with AGP. The graphics-card side AGP support isn't a problem if you have proper specs for the card (though that's a big "if").
Sun, IBM, HP and SGI all use Advanced RISC processors.
Not quite anymore, actually. SGI spun off MIPS into its own company and is now building servers based on Intel chips with SGI-style motherboards running Windows NT, if I understand correctly.
HP partnered with Intel to develop the Merced and announced intentions to abandon its PA-RISC line. Fortunately they've been having second thoughts, and have deferred killing PA-RISC for the time being.
Hopefully this is an abberation and not a trend. However, only time will tell.
I'm mainly interested in chip news and graphics news, though. For more general news or for specific news on other topics, you'd have to check other sites.
In a similar vein, would not firing a UV laser at an approaching thundercloud force it to discharge? You'd need a large Faraday cage/lightning rod around the laser to protect it, but otherwise lightning storms could be controlled and directed.
This has been thought of, and is in development as a way of keeping lightning away from airports. There was an article in Scientific American about this a while back.
The laser doesn't need to be shielded; the beam is focused instead of parallel, which means that only air at the focal point is ionized (a similar scheme is described above). A series of pulses are emitted as the laser is swept from ground to sky (or vice versa), and you wind up (hopefully) with an ionized trail at a distance from the laser.
But does any one know how well the SMP will be on K7?
Based on what I've read here, the K7 will have extremely good SMP support, assuming that there are chipsets for it. 16 processors was the limit that I heard stated, IIRC.
OTOH, the K7 was supposed to be fairly expensive, and its actual performance gains over a PIII remain murky. We'll see what happens when it ships.
But on this deal, why not 2 to a board, making a 4-way system? Can that be possible?
Based other messages I've read here, I doubt that would work. The Celeron is essentially a PII, and that can only support dual processors due to a deliberate limitation imposed by Intel. For quad processors or better, you'd need Xeons.
I bought a two processor mainboard and I've got one PII-400 in it. The PII-400 is now cheap enough that I COULD get a second one, but for the same money I could get two Celerons and have a PII-400 left over.
Unless you have an immediate use for the leftover PII-400, I'd suggest getting the second PII-400 instead of celerons, as you'll have more cache. Just my opinion.
Ok, this is sounding a bit more realistic. Thanks for the information. Commentary is as follows.
The EE:... 16 KB icache, 8 KB dcache, 16 K SRAM
It'll starve its data cache pretty quickly, but the 16K of scratch RAM should easily make up for that. This looks nice.
has two 128 bit wide SIMD FP vector processors, each with four 32 bit FMACs and one FP divider. Each vector processor can perform 19 macs and one divide every 7 clocks.
Good luck keeping those pipes saturated, but this should make transformations a lot easier. Instruction processing will be the limiting factor, not FP performance.
The GS: 279 mm2 0.25 um chip with 42.7 million transistors
At 0.25 micron, this will be a bugger to fabricate. The bright side is that a lot of those transistors are DRAM, which can be made fault-tolerant. When they ramp up to 0.18 micron, yields and raw production will both get considerably better.
includes 16 pixel processors and 4 MB of multiport DRAM
Now, the question is whether the DRAM is multiported _enough_ to drive that many rendering pipes. The main load on it will be texel requests (as the most productive use of it is a texel cache - a Very Useful Thing to have multiported RAM for).
and 512 bit wide texture reads
This is a *bad* thing - if you only need one texel of information, you're still reading in 512 bits. In practice, the rendering pipes in the graphics engine will have their own individual texel caches with finer granularity, but your texel bandwidth under real conditions won't be anywhere close to the theoretical maximum. Still nothing to sneeze at by a long shot, though.
This was probably an architectural tradeoff. Finer cache granularity would have involved more silicon and a lower cache capacity.
So, this looks like a well-designed system that integrates two MIPS cores, some well-designed FP extensions, a good graphics ASIC, and some cache into a powerful unit. The hype is still hype, but there is something decent behind it.
Better. Sustained transformed, not rendered, though.
16 Mpoly/s Bezier surface patches
Peak or sustained? Set up or rendered?
75 Mpoly/s peak rendering
I hope they've dropped a decimal point, because that's higher than their peak transformation rate. 7.5 million polys per second rendered would be believeable and very impressive (conventional graphics cards process at most a few million _submitted_, IIRC).
2400 Mpixel/s fill with z buffering + alpha blending * 1200 Mpixel/s fill with Z + alpha + texture
Without texturing, the 2.4 Gpixels/sec applies only to screen/z clearing and Gouraud-shaded light maps, then. 1.4 Gpixels/second is still nothing to sneeze at. In fact, it's sufficiently excessive that I suspect that other parts of the rendering pipe will be the bottlenecks, as opposed to fill rate. Triangle setup for small polygons or texel fetches for large polygons is my guess.
In any event, it looks nice, and I look forward to seeing how it behaves in practice. Graphics card manufacturers could learn a lesson from studying this system architecture (putting a DSP or FP-optimized processor on to a card with the graphics ASIC isn't hard, but isn't done very much on the consumer end yet).
Thanks for the correction: silicon-based chips with copper substrates, NOT copper-based chips.
I hope you mean interconnects instead of substrates...
"They would be bulkier, and wouldn't be faster, because while electrical signals propagate slower than light, they would have a much shorter distance to travel. If you try using light with a much shorter wavelength, you wind up destroying your substrate (the photon energy must remain lower than the energy required to dislodge an atom in in the device)."
An electro-optical device does not use a silicon substrate, nor does it need the interconnect metals that we see today. Furthermore, the materials used for the device's internal parts and casing allow researchers to experiment with light wavelengths outside the visible spectrum.
My argument holds no matter what materials you use to build the optical device and no matter what processes are used to fabricate it. Whatever you do, you just _can't_ get the feature size of optical devices much smaller than the wavelength of the light used, or signals bleed from one computing element into another. Likewise, no matter what material you make the device out of, you can't have photons with an energy of more than a few eV, because that is the typical binding energy of valence electrons in atoms. If you decide to use deep UV or what-have-you, your device _will_ degrade due to atoms being dislodged and bonds being broken, no matter what it's made of.
But remember: Prof. Shamir's theoretical device is NOT A CPU! It is an "electro-optical sieving device"
How does this affect my points?
Because of its narrow function, the "TWINKLE" box will likely have a much cleaner, simpler design
This is true of any special-purpose computer. What of it?. See Deep Crack for an example, or look at DSP designs (they elminate a lot of the scheduling cruft that conventional chips have, with the cost of requiring the compiler to optimize code for them).
Just looks at current electro-optical devices used for various computing needs today: they have simple, elegant designs, fewer parts and are often smaller than their fully electrical counterparts operating at the same data transmission rates.
An electro-optical component is for the reasons mentioned previously bulkier than a transistor. They also, as mentioned previously, suffer from the limitations of both electrical and optical systems, because they incorporate both. Electro-optical components are indeed very useful for a moderate-sized set of applications; however, they aren't magical.
TWINKLE attacks by factoring. This is useful for most asymmetric algorithms but not for symmetric algorithms which do not use primes maths.
However, the original question was about the timings cited in the TWINKLE article:
I'm mildly confused by the timings, so how long would it take a decently powerful (as in, PII 300) machine hooked in to one of these devices to crack that?
My response stands for that, though as you point out these timings don't apply to other classes of encryption.
A few points in your post puzzle me; I'd appreciate it if you could elaborate on what you mean:
Today's "conventional PC" uses silicon-based CPU technology, but that will change in a few years when IBM begins to mass-produce copper-based chips.
IBM has already demonstrated chips with copper _interconnects_, and many manufacturers plan to use this technology, but I've never heard of using copper as a _substrate_. Conventional chips use a silicon _substrate_ and aluminum interconnects. What IBM technology are you referring to?
An "electro-optical" computational device is the next paradign shift in computer engineering. By transmitting data via light (LEDs!!!), the current CPU problems with heat, electromagnetic interference (EMI) and wafer size all disappear.
I'm afraid that this is not strictly true. In fact, feature size for optical components would be a big problem. Optical devices can't have features much smaller than a wavelength of light. For visible light, this is on the order of 0.5 microns. Electrical devices, like conventional integrated circuit chips, can have features that are much smaller. This tends to outweigh most of the advantages of using optical "chips", should such chips be developed. They would be bulkier, and wouldn't be faster, because while electrical signals propagate slower than light, they would have a much shorter distance to travel. If you try using light with a much shorter wavelength, you wind up destroying your substrate (the photon energy must remain lower than the energy required to dislodge an atom in in the device).
Heat dissipation is and will remain a problem for electrical devices, but photons get absorbed too.
Electro-optical devices, OTOH, get the worst of both worlds. The only situation in which they're really practical is when you need to send signals over a (relatively) large distance without much degradation, as is apparently the case with the computer being built here.
I'm mildly confused by the timings, so how long would it take a decently powerful (as in, PII 300) machine hooked in to one of these devices to crack that?
A very long time, though still just a linear factor longer. Your computer has to solve one hell of a huge matrix problem. This requires enough RAM to hold the matrix and any working data (gigabytes or _more_; see the article), and time proportional to the cube of the matrix size (or possibly better if you're using something other than Gauss-Jordan reduction).
They used a supercomputer to do the matrix solving. If your machine has n times fewer bogoMIPs, then it will take n times longer, assuming that you can support the required RAM.
Assuming that it is the matrix solution and not the sieving that limits the solution time. This would probably be the case if you're using a PC to process the matrix.
Could you point me to more info on the P=NP concept? Or if not, provide an explaination?
"P" and "NP" are categories of problem. P problems can by solved relatively quickly, but it isn't known if NP problems can or can't.
A problem is a "P" type problem (is "in P") if it can be solved in polynomial time or better; that is, the number of steps required to produce a solution for input of n bits is proportional to (or better than) n^k, for some _constant_ k. This might be a solution that's O(n), or O(n^2), or O(n^534), but it's still polynomial (or better, for something like O(log n)).
A problem is an "NP" type problem (is "in NP") if you can prove that your solution is correct in polynomial time. It might take polynomial time to solve or it might not, but you can prove the answer in polynomial time. The factoring problem is a good example of a problem in NP. No presently known way exists of finding the factors of a number in time proportional to a polynomial of the number of bits, but you can prove that two numbers (say a and b) _are_ the factor of a larger number (X) just by multiplying a and b and seeing if you get X. The multiplication time is proportional to (or better than) a polynomial of the number of bits in X (it's proportional to X^2 for the straightforward way). So, NP problems can be ugly, but there is a limit to how ugly they can get.
A problem that is "outside of NP" can't be solved in polynomial time (otherwise it would be in P) and has solutions that can't be checked in polynomial time (otherwise it would be in NP). I can't think of a good example off the top of my head, but they exist.
P is in NP; you can prove that a polynomial-time answer is correct just by solving the problem again. However, nobody knows if _all_ problems in NP can also be solved in polynomial time. This would mean that P = NP (the two sets of problems are the same, because everything in both of them is in P). A proof that P = NP would prove that any encryption scheme that depends on a trap-door function in NP is intrinsically weak. On the other hand, a proof that P != NP would prove that anything based on an NP-complete trapdoor function (I'll get back to this) is sound against anything short of a quantum computing attack. This is especially of interest to people who deal with prime numbers, because the factoring problem is in NP, and a P-time factoring algorithm would be a Very Useful Thing.
NP-complete problems are problems that are in NP, but that are at least as hard as anything else in NP (or more accurately, any other problem in NP can be reduced in polynomial-time to this problem). An NP-hard problem, for reference, is a problem like this that may or may not even be in NP at all (it's just at least as hard as anything in NP).
This brings up another very important point. All problems that are in NP can be reduced in polynomial time to any NP-complete problem. This means that if you can solve even one of the NP-complete problems in polynomial time, you can solve them all in polynomial time (just with worse exponents). An algorithm that solves an NP-complete problem, or a proof that no such algorithm exists, is one of the holy grails of mathematics, as it would settle the question of whether or not P = NP.
And I hope you've been taking notes, because there'll be a short quiz next period. O:) [ducks!]
Slashdot Mirror
It just ain't possible.
Not strictly true. All that your example shows is that you would not be able to kill your former self. Two of the several solutions that I've heard postulated are:
Under this system, you would certainly not be able to kill yourself, becuase you didn't (you survived to travel backwards in time, didn't you?). This physically corresponds to limiting (drastically) the number of possible events that can occur within a loop of spacetime that folds back on itself in the time direction. This in turn means that such loops are entropically very unfavourable, but they could still in principle occur if a greater increase in entropy happened elsewhere.
This refers to the "multiple histories" interpretation of quantum dynamics. Under this system, when you flip a coin, it lands on both sides - just in different universes. What actually happens is that all possible ways for a probability waveform to collapse happen, in different universes. If you travel back in time, you arrive in another universe, that looks a lot like the one you remember from that time - but in which a time traveller spontaneously appeared and killed the person who would have been you in your universe. This system doesn't impose entropic limits, but how exactly you travel between parallel universes is left as an exercise.
Both of these systems avoid the paradox that you menion.
Actually, that's not accurate, if I understand correctly. As the universe contracts, GPE will certainly become more negative, but as a result of this kinetic energy goes _up_ for everything that's contracting. Thus, the universe gets hotter again.
(1) Objects far apart have more energy than objects close together (because it takes energy to separate them)
(2) The universe is expanding.
This just is just a statement that the total kinetic and rest energy of the objects in the universe has the same magnitude as the total gravitational potential energy of all objects in the universe. This is actually what _causes_ the universe to heat up as it contracts (and cool as it expands; the microwave background is a good example of this).
As an aside, the jury is still out as to whether the universe is really flat or not (i.e. whether or not this relation holds). We usually assume so because it answers a lot of questions, but we're having a hard time proving it.
Actually, no. If only electrons and positrons and photons existed, then you might be able to draw a Feynman diagram with one line representing all electrons and protons, but beta decay takes care of that. A quark can decay into another quark, an electron, and an antineutrino. This provides the start of a new electron line. Similarly, a quark can decay into a positron, another quark, and a neutrino. This provides the end of an electron line. In principle, the reverse reactions could occur as well.
It's adjustable. If I understand correctly, "Alcubierre Space" is just one possible (and geometrically simple) configuration of spacetime that allows an object to (for practical purposes) "move" faster than light with respect to its surroundings. This is an extension and modification of those results that uses a more complicated geometry but has fewer practical problems.
There was an excellent example a few months back. In one of the Free vs. Proprietary Holy Wars, an AC posted details of a lawsuit that his company was involved in as a thought-provoking case study. He (or she) would have been fired for doing this non-anonymously.
From what I can see reading at -1, maybe a third of AC posts are garbage, and most of the rest are at best average, but I see no reason to get rid of AC just because of the actions of a handful of twits. This is the second time that a lone idiot has spammed a thread. A solution that only attacks those twits would be nice.
Both banning IPs and limiting AC posts from an IP run into the problem of ISPs allocating IPs dynamically, and firewalls remapping users to a single IP address. However, it still might be the best solution (I'm open to other suggestions).
Or log IP and time for each post, so that Rob can contact the ISPs of abusers and get them LARTed. But that would be a lot of work for Rob.
It's here in the form of rule-of-the-masses; if a moderator unjustly scores something, then other moderators will reverse it. This only applies if most moderators are fair, but it seems to have worked fairly well so far IMO.
Addendum: This works for conventional DRAM too. However, I gather that it isn't done (except possibly for Virtual Channel Memory). A static transistor instead of a capacitor would still give you better signal strength, though.
This is probably not true. Precharge and amplify has less to do with nature of the memory cell,
but are used to speed up the access time of a RAM device. Even today's fast static-RAMs use
precharge and amplify circuits to speed things up.
I was referring to the sense amplifiers, which take a while to produce stable readings if I understand correctly. AFAIK precharge/amplify assisted circuits of the type you describe are faster, because they have a signal continuously driving them and so are less sensitive to noise. I could be wrong about this, but I don't think so.
Also in a large (eg, Gbit arrays) the poor little super-small transistor that is attached to
a bit of the memory in the middle the array has little hope of driving a big long piece of
bit-sense wire out to the edge of the array without the help of an amplifier
If you connected hundreds or thousands of transistors into a column, this would certainly be true. However, I certainly hope that chip designers wouldn't do this. Arrange a single RAM chip into multiple banks with a column height of 16 or 32 cells. Most of your die space is still taken up by memory, and your transistors only have the capacitance of a handful of other drains to worry about. This could be driven without amplification, and would still be quite fast. You even get many free row caches (one per bank).
This actually isn't terribly relevant to the topic. There was, IIRC, only a single mention of the new type of RAM developed, as a tangential point. While the post was interesting, I can see why it was rated down.
Nothing remotely amusing can be allowed past the moderators though.
For all of the whining that goes on, I have yet to see something moderated down that didn't deserve to be. I do read at -1, so I see everything.
?. This is completely different from the definition that I heard. The type of "bubble memory" that I know about stores data in isolated magnetic domains (bubbles) that can be physcially moved around within a crystal. High density, but serial access (though you can get around that to some degree). I'm told that it was also slow and sensitive to external magnetic fields, but other sources say that those problems were solved.
True. However, if I understand correctly, you won't be able to use system memory for texturing without explicit AGP support. This is one of the primary benefits of AGP (especially with cards that let you read triangle setup data from AGP memory; bus-limit bottlenecks just got a lot wider).
I don't know what kind of support this requires OS-side, but the previous post implied that AGP chipset specs are needed. Certainly the OS needs to be able to lock and unlock sections of memory for use with AGP. The graphics-card side AGP support isn't a problem if you have proper specs for the card (though that's a big "if").
Not quite anymore, actually. SGI spun off MIPS into its own company and is now building servers based on Intel chips with SGI-style motherboards running Windows NT, if I understand correctly.
HP partnered with Intel to develop the Merced and announced intentions to abandon its PA-RISC line. Fortunately they've been having second thoughts, and have deferred killing PA-RISC for the time being.
Hopefully this is an abberation and not a trend. However, only time will tell.
"You can please some of the people all of the time, or [...]
The variant that I heard had "fool" instead of "please". I've seen this in many places, so it seems to be in fairly widespread use.
Sharkey Extreme's "news" section is also good. The URL is http://www.sharkyextreme.com/news.shtml .
I'm mainly interested in chip news and graphics news, though. For more general news or for specific news on other topics, you'd have to check other sites.
This has been thought of, and is in development as a way of keeping lightning away from airports. There was an article in Scientific American about this a while back.
The laser doesn't need to be shielded; the beam is focused instead of parallel, which means that only air at the focal point is ionized (a similar scheme is described above). A series of pulses are emitted as the laser is swept from ground to sky (or vice versa), and you wind up (hopefully) with an ionized trail at a distance from the laser.
Based on what I've read here, the K7 will have extremely good SMP support, assuming that there are chipsets for it. 16 processors was the limit that I heard stated, IIRC.
OTOH, the K7 was supposed to be fairly expensive, and its actual performance gains over a PIII remain murky. We'll see what happens when it ships.
Based other messages I've read here, I doubt that would work. The Celeron is essentially a PII, and that can only support dual processors due to a deliberate limitation imposed by Intel. For quad processors or better, you'd need Xeons.
Unless you have an immediate use for the leftover PII-400, I'd suggest getting the second PII-400 instead of celerons, as you'll have more cache. Just my opinion.
The EE:
It'll starve its data cache pretty quickly, but the 16K of scratch RAM should easily make up for that. This looks nice.
has two 128 bit wide SIMD FP vector processors, each with four 32 bit FMACs and one FP divider. Each vector processor can perform 19 macs and one divide every 7 clocks.
Good luck keeping those pipes saturated, but this should make transformations a lot easier. Instruction processing will be the limiting factor, not FP performance.
The GS: 279 mm2 0.25 um chip with 42.7 million transistors
At 0.25 micron, this will be a bugger to fabricate. The bright side is that a lot of those transistors are DRAM, which can be made fault-tolerant. When they ramp up to 0.18 micron, yields and raw production will both get considerably better.
includes 16 pixel processors and 4 MB of multiport DRAM
Now, the question is whether the DRAM is multiported _enough_ to drive that many rendering pipes. The main load on it will be texel requests (as the most productive use of it is a texel cache - a Very Useful Thing to have multiported RAM for).
and 512 bit wide texture reads
This is a *bad* thing - if you only need one texel of information, you're still reading in 512 bits. In practice, the rendering pipes in the graphics engine will have their own individual texel caches with finer granularity, but your texel bandwidth under real conditions won't be anywhere close to the theoretical maximum. Still nothing to sneeze at by a long shot, though.
This was probably an architectural tradeoff. Finer cache granularity would have involved more silicon and a lower cache capacity.
So, this looks like a well-designed system that integrates two MIPS cores, some well-designed FP extensions, a good graphics ASIC, and some cache into a powerful unit. The hype is still hype, but there is something decent behind it.
Performance claims: 6.2 GFLOP/s peak * 66 Mpoly/s transform peak
"peak" says it all.
36 Mpoly/s transform sustained
Better. Sustained transformed, not rendered, though.
16 Mpoly/s Bezier surface patches
Peak or sustained? Set up or rendered?
75 Mpoly/s peak rendering
I hope they've dropped a decimal point, because that's higher than their peak transformation rate. 7.5 million polys per second rendered would be believeable and very impressive (conventional graphics cards process at most a few million _submitted_, IIRC).
2400 Mpixel/s fill with z buffering + alpha blending * 1200 Mpixel/s fill with Z + alpha + texture
Without texturing, the 2.4 Gpixels/sec applies only to screen/z clearing and Gouraud-shaded light maps, then. 1.4 Gpixels/second is still nothing to sneeze at. In fact, it's sufficiently excessive that I suspect that other parts of the rendering pipe will be the bottlenecks, as opposed to fill rate. Triangle setup for small polygons or texel fetches for large polygons is my guess.
In any event, it looks nice, and I look forward to seeing how it behaves in practice. Graphics card manufacturers could learn a lesson from studying this system architecture (putting a DSP or FP-optimized processor on to a card with the graphics ASIC isn't hard, but isn't done very much on the consumer end yet).
...But the question was _about_ times to crack RC4-128. I withdraw my comments... Doh.
I hope you mean interconnects instead of substrates...
"They would be bulkier, and wouldn't be faster, because while electrical signals propagate slower than light, they would have a much shorter distance to travel. If you try using light with a much shorter wavelength, you wind up destroying your substrate (the photon energy must remain lower than the energy required to dislodge an atom in in the device)."
An electro-optical device does not use a silicon substrate, nor does it need the interconnect metals that we see today. Furthermore, the materials used for the device's internal parts and casing allow researchers to experiment with light wavelengths outside the visible spectrum.
My argument holds no matter what materials you use to build the optical device and no matter what processes are used to fabricate it. Whatever you do, you just _can't_ get the feature size of optical devices much smaller than the wavelength of the light used, or signals bleed from one computing element into another. Likewise, no matter what material you make the device out of, you can't have photons with an energy of more than a few eV, because that is the typical binding energy of valence electrons in atoms. If you decide to use deep UV or what-have-you, your device _will_ degrade due to atoms being dislodged and bonds being broken, no matter what it's made of.
But remember: Prof. Shamir's theoretical device is NOT A CPU! It is an "electro-optical sieving device"
How does this affect my points?
Because of its narrow function, the "TWINKLE" box will likely have a much cleaner, simpler design
This is true of any special-purpose computer. What of it?. See Deep Crack for an example, or look at DSP designs (they elminate a lot of the scheduling cruft that conventional chips have, with the cost of requiring the compiler to optimize code for them).
Just looks at current electro-optical devices used for various computing needs today: they have simple, elegant designs, fewer parts and are often smaller than their fully electrical counterparts operating at the same data transmission rates.
An electro-optical component is for the reasons mentioned previously bulkier than a transistor. They also, as mentioned previously, suffer from the limitations of both electrical and optical systems, because they incorporate both. Electro-optical components are indeed very useful for a moderate-sized set of applications; however, they aren't magical.
However, the original question was about the timings cited in the TWINKLE article:
I'm mildly confused by the timings, so how long would it take a decently powerful (as in, PII 300) machine hooked in to one of these devices to crack that?
My response stands for that, though as you point out these timings don't apply to other classes of encryption.
Today's "conventional PC" uses silicon-based CPU technology, but that will change in a few years when IBM begins to mass-produce copper-based chips.
IBM has already demonstrated chips with copper _interconnects_, and many manufacturers plan to use this technology, but I've never heard of using copper as a _substrate_. Conventional chips use a silicon _substrate_ and aluminum interconnects. What IBM technology are you referring to?
An "electro-optical" computational device is the next paradign shift in computer engineering. By transmitting data via light (LEDs!!!), the current CPU problems with heat, electromagnetic interference (EMI) and wafer size all disappear.
I'm afraid that this is not strictly true. In fact, feature size for optical components would be a big problem. Optical devices can't have features much smaller than a wavelength of light. For visible light, this is on the order of 0.5 microns. Electrical devices, like conventional integrated circuit chips, can have features that are much smaller. This tends to outweigh most of the advantages of using optical "chips", should such chips be developed. They would be bulkier, and wouldn't be faster, because while electrical signals propagate slower than light, they would have a much shorter distance to travel. If you try using light with a much shorter wavelength, you wind up destroying your substrate (the photon energy must remain lower than the energy required to dislodge an atom in in the device).
Heat dissipation is and will remain a problem for electrical devices, but photons get absorbed too.
Electro-optical devices, OTOH, get the worst of both worlds. The only situation in which they're really practical is when you need to send signals over a (relatively) large distance without much degradation, as is apparently the case with the computer being built here.
A very long time, though still just a linear factor longer. Your computer has to solve one hell of a huge matrix problem. This requires enough RAM to hold the matrix and any working data (gigabytes or _more_; see the article), and time proportional to the cube of the matrix size (or possibly better if you're using something other than Gauss-Jordan reduction).
They used a supercomputer to do the matrix solving. If your machine has n times fewer bogoMIPs, then it will take n times longer, assuming that you can support the required RAM.
Assuming that it is the matrix solution and not the sieving that limits the solution time. This would probably be the case if you're using a PC to process the matrix.
"P" and "NP" are categories of problem. P problems can by solved relatively quickly, but it isn't known if NP problems can or can't.
A problem is a "P" type problem (is "in P") if it can be solved in polynomial time or better; that is, the number of steps required to produce a solution for input of n bits is proportional to (or better than) n^k, for some _constant_ k. This might be a solution that's O(n), or O(n^2), or O(n^534), but it's still polynomial (or better, for something like O(log n)).
A problem is an "NP" type problem (is "in NP") if you can prove that your solution is correct in polynomial time. It might take polynomial time to solve or it might not, but you can prove the answer in polynomial time. The factoring problem is a good example of a problem in NP. No presently known way exists of finding the factors of a number in time proportional to a polynomial of the number of bits, but you can prove that two numbers (say a and b) _are_ the factor of a larger number (X) just by multiplying a and b and seeing if you get X. The multiplication time is proportional to (or better than) a polynomial of the number of bits in X (it's proportional to X^2 for the straightforward way). So, NP problems can be ugly, but there is a limit to how ugly they can get.
A problem that is "outside of NP" can't be solved in polynomial time (otherwise it would be in P) and has solutions that can't be checked in polynomial time (otherwise it would be in NP). I can't think of a good example off the top of my head, but they exist.
P is in NP; you can prove that a polynomial-time answer is correct just by solving the problem again. However, nobody knows if _all_ problems in NP can also be solved in polynomial time. This would mean that P = NP (the two sets of problems are the same, because everything in both of them is in P). A proof that P = NP would prove that any encryption scheme that depends on a trap-door function in NP is intrinsically weak. On the other hand, a proof that P != NP would prove that anything based on an NP-complete trapdoor function (I'll get back to this) is sound against anything short of a quantum computing attack. This is especially of interest to people who deal with prime numbers, because the factoring problem is in NP, and a P-time factoring algorithm would be a Very Useful Thing.
NP-complete problems are problems that are in NP, but that are at least as hard as anything else in NP (or more accurately, any other problem in NP can be reduced in polynomial-time to this problem). An NP-hard problem, for reference, is a problem like this that may or may not even be in NP at all (it's just at least as hard as anything in NP).
This brings up another very important point. All problems that are in NP can be reduced in polynomial time to any NP-complete problem. This means that if you can solve even one of the NP-complete problems in polynomial time, you can solve them all in polynomial time (just with worse exponents). An algorithm that solves an NP-complete problem, or a proof that no such algorithm exists, is one of the holy grails of mathematics, as it would settle the question of whether or not P = NP.
And I hope you've been taking notes, because there'll be a short quiz next period. O:) [ducks!]