you should also consider you're doing test coverage analysis based on finding faults... not a deliberately hidden function.... it would be awfully easy to write a few lines of RTL that are disabled by "test enable" signals to hide themselves from test patterns....
I think its an over-exageration to say that domestic chips are impossible... where were the first 2 production 45 nm fabs built again? its possible to build anything DOD needs domestically.... its just not possible to do that while leveraging the economic benefits of the global electronics industry.
uhhh usually they refer to alpha particles.... you know, helium nuclei.... those tend to not be uniformly distributed... but "lumpy". Alpha particles can have a couple of MEV of energy... but it may only take 1 MEV of energy to "upset" the smallest of latch structures.
I know chip designers who had to spend man-months analysing which unprotected latches held which system critical bits and how susceptible each latch type was to radiation.... that was 90 nm.... imagine a 45 nm part.
there is also a pretty well known incident of sun servers that shipped without ECC memory that had a huge reliability problem... the only solution was to move all the susceptible parts to the basement/caves...
yes... mainframes do this already.... alot of time people talk about "cosmic background radiation" (which does occur) but historically another big source of radiation is small ammounts of radioactive heavy metals sneaking into solders... which can be more impactful just based on proximity to silicon.
I haven't read the patent.... but I wonder if there are issues with the detector location vs where the event occurs... how many detectors does it take to cover a 20X20 mm chip? is it really worth that real-estate in the dead center of the chip? ( I think this is why traditionally cross-checking or voting is the prefered method)
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you should also consider you're doing test coverage analysis based on finding faults... not a deliberately hidden function.... it would be awfully easy to write a few lines of RTL that are disabled by "test enable" signals to hide themselves from test patterns....
I think its an over-exageration to say that domestic chips are impossible... where were the first 2 production 45 nm fabs built again? its possible to build anything DOD needs domestically.... its just not possible to do that while leveraging the economic benefits of the global electronics industry.
uhhh usually they refer to alpha particles.... you know, helium nuclei.... those tend to not be uniformly distributed... but "lumpy". Alpha particles can have a couple of MEV of energy... but it may only take 1 MEV of energy to "upset" the smallest of latch structures. I know chip designers who had to spend man-months analysing which unprotected latches held which system critical bits and how susceptible each latch type was to radiation.... that was 90 nm.... imagine a 45 nm part. there is also a pretty well known incident of sun servers that shipped without ECC memory that had a huge reliability problem... the only solution was to move all the susceptible parts to the basement/caves...
I haven't read the patent.... but I wonder if there are issues with the detector location vs where the event occurs... how many detectors does it take to cover a 20X20 mm chip? is it really worth that real-estate in the dead center of the chip? ( I think this is why traditionally cross-checking or voting is the prefered method)